Asymmetric Semiconductor Patterns via Dual Photolithography Masks
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The reduction of critical dimension (CD) in semiconductor device design leads to electrical or physical shorts between discrete elements, deteriorating device characteristics and interconnection capabilities, complicating the fabrication process and increasing production costs.
Innovation Solution
A photolithography process using two masks to form asymmetric semiconductor patterns, where the first mask comprises patterns at cross points of horizontal and vertical lines, and the second mask has patterns on every other horizontal line, simplifying the process and maintaining price competitiveness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If multiple masks and photolithography processes are used to form asymmetric patterns, then the fine patterning capability is improved, but the process complexity and production cost increase
Solution Approach 1:
The patent divides the asymmetric pattern formation into two separate photolithography masks: a first mask for forming initial patterns and a second mask for forming asymmetric patterns on alternate horizontal lines. This segmentation allows each mask to be optimized for its specific function, simplifying the overall process while maintaining fine patterning capability
Solution Approach 2:
The patent introduces a dimensional approach by specifying that the second mask forms patterns on alternate horizontal lines relative to the first mask. This dimensional specification (every other horizontal line) provides a systematic method for creating asymmetric patterns without requiring complex multi-step processes
2Manufacturing precision
If multiple masks and photoresist layers are used to form asymmetric patterns, then the patterning precision is improved, but the production cost increases
Solution Approach 1:
The patent extracts the asymmetric pattern formation requirement from a complex multi-photoresist process and implements it through a streamlined two-mask approach. By taking out only the essential masking steps needed for asymmetric patterns, the process achieves high precision while reducing photoresist layer complexity and associated costs
3Productivity
If the critical dimension is reduced to form smaller patterns, then the device performance is improved, but the risk of electrical or physical shorts increases
Solution Approach 1:
The patent applies local quality by forming patterns at specific locations (alternate horizontal lines) rather than uniformly across the substrate. This localized approach to asymmetric pattern formation allows precise control over where patterns are created, maintaining adequate spacing to prevent shorts while achieving the required small critical dimensions for improved device performance
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach simplifies the semiconductor formation process, reduces production costs, and maintains device performance by effectively forming asymmetric patterns with smaller CD without compromising device characteristics.
Implementation Method 1
A first photolithography mask is transferred to the photoresist layer. A second photolithography mask is transferred to the photoresist layer. The first photolithography mask and the second photolithography mask transfer a composite aerial image of the first semiconductor pattern and the second semiconductor pattern that define the asymmetric semiconductor pattern to the photoresist layer
Data Source
AI summary
There are provided methods of performing a photolithography process for forming asymmetric semiconductor patterns and methods of forming a semiconductor device using the same. These methods provide a way of forming asymmetric semiconductor patterns on a photoresist layer through two exposure processes. To this end, a semiconductor substrate is prepared. A planarized insulating interlayer and a photoresist layer are sequentially formed on the overall surface of the semiconductor substrate. A first semiconductor pattern of a photolithography mask is transferred to the photoresist layer, thereby forming a photoresist pattern on the photoresist layer. A second semiconductor pattern of a second photolithography mask is continuously transferred to the photoresist layer, thereby forming a second photoresist pattern on the photoresist layer. An etching process is performed on the planarized insulating interlayer to expose the semiconductor substrate, using the first photoresist pattern and the second photoresist pattern as etch masks.