Asymmetric Source/Drain Contact for Multi-Gate Transistor
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Solution Overview
Problem
Current semiconductor devices face challenges in achieving improved operational performance and reliability, particularly in multi-gate transistors where scaling and reducing short channel effects are difficult.
Innovation Solution
The semiconductor device design includes a fin-shaped pattern with asymmetric contact side walls that do not vertically overlap the gate structures, allowing for enhanced current control and reduced short channel effects through a specific trench and gate structure configuration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If a multi-gate transistor uses a three-dimensional channel for scaling, then current control capability is improved, but short channel effects still affect the channel potential
Solution Approach 1:
The contact structure employs asymmetric side wall configurations where the first side wall has a different profile than the second side wall. This asymmetry allows optimized electrical contact to the source/drain region while maintaining proper spacing from the gate structures, thereby improving current control capability while mitigating short channel effects through controlled geometric asymmetry in the contact region
Solution Approach 2:
The invention transitions from a conventional planar contact structure to a three-dimensional contact structure with vertical side walls extending into the interlayer insulating films. This dimensional change enables the contact to reach the source/drain region more effectively while the asymmetric positioning prevents vertical overlap with gate structures, simultaneously improving current control and reducing short channel effects
2Reliability
If the contact is positioned to connect to the source/drain region, then electrical connectivity is achieved, but vertical overlap with gate structures causes performance degradation
Solution Approach 1:
The contact structure employs asymmetric side wall configurations where the first side wall has a different profile than the second side wall. This asymmetry allows optimized electrical contact to the source/drain region while maintaining proper spacing from the gate structures, thereby improving current control capability while mitigating short channel effects through controlled geometric asymmetry in the contact region
Solution Approach 2:
The contact structure exhibits different local geometries at its boundaries: the first side wall is configured for optimal electrical contact with the source/drain region, while the second side wall is configured to maintain clearance from gate structures. This local differentiation of contact properties enables simultaneous achievement of reliable electrical connectivity and avoidance of gate interference
Data Source
AI summary
A semiconductor device includes a lower interlayer insulating film including a first trench and a second trench adjacent each other; a first gate structure within the first trench and extending in a first direction; a second gate structure within the second trench and extending in the first direction; a source/drain adjacent the first gate structure and the second gate structure; an upper interlayer insulating film on the lower interlayer insulating film; and a contact connected to the source/drain, the contact in the upper interlayer insulating film and the lower interlayer insulating film, wherein the contact includes a first side wall and a second side wall, the first side wall of the contact and the second side wall of the contact are asymmetric with each other, and the contact does not vertically overlap the first gate structure and the second gate structure.