Asymmetric Source Drain Contacts for Transistor Threshold Voltage Control
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Solution Overview
Problem
In semiconductor devices, particularly in transistors with gate widths of 1 μm or less, variations in threshold voltage are significant due to crystal defects caused by stress generated in the active regions from the alignment of source/drain contacts, leading to reduced transistor performance.
Innovation Solution
The source/drain contacts are arranged with elongated bottom surfaces that are not aligned in a straight line with the extension direction of the active region, applying stress in different directions to reduce crystal defects and minimize threshold voltage variations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If source/drain contacts are aligned in a straight line with the active region extension direction, then manufacturing is simplified, but crystal defects increase and threshold voltage varies significantly
Solution Approach 1:
The source/drain contacts are intentionally arranged asymmetrically relative to the active region extension direction. Instead of aligning the contacts in a straight line with the active region, they are positioned at offset locations, creating an asymmetric configuration that reduces crystal defects and suppresses threshold voltage variation while maintaining manufacturing feasibility.
Solution Approach 2:
The contact arrangement moves from a one-dimensional straight-line alignment to a two-dimensional offset configuration. By positioning contacts at lateral offsets from the active region extension line, the solution introduces a spatial dimension change that effectively distributes stress and reduces crystal defects without significantly complicating the manufacturing process.
2Length of moving object
If gate width is reduced to 1 μm or less, then device size is reduced, but threshold voltage variation increases due to stress concentration
Solution Approach 1:
The offset arrangement of source/drain contacts creates localized stress distribution patterns that are beneficial for small gate widths. By positioning contacts at specific offset locations, the stress is distributed in a controlled manner within the active region, preventing stress concentration that would otherwise cause significant threshold voltage variation in narrow gate devices.
Data Source
AI summary
According to one embodiment, a semiconductor device includes a transistor having a diffusion layer extending along a surface of a substrate and a gate electrode arranged above the diffusion layer; and contacts having elongated bottom surfaces connected to the diffusion layer on both sides of the gate electrode, in which the contacts are arranged so that the bottom surfaces of the contacts are not aligned in a straight line with an extension direction of the diffusion layer.