Asymmetric Epitaxial Source-Drain Layout for Low-Parasitic Nanowire FETs
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Solution Overview
Problem
Conventional fabrication processes for integrated circuits face challenges in scaling to the 10 nanometer node or sub-10 nanometer node due to variability and constraints on semiconductor processes, limiting the performance and efficiency of multi-gate transistors.
Innovation Solution
Implementing asymmetric epitaxial source or drain arrangements with differentiated gate spacers and contact processing, including backside power delivery and self-aligned access features, to reduce parasitic capacitance and resistance, and enable efficient integration of nanowire transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional fabrication processes are used for scaling, then manufacturing simplicity is maintained, but manufacturing precision deteriorates at 10 nanometer node or sub-10 nanometer node
Solution Approach 1:
The fabrication process is divided into separate front-side and backside processing sequences. The backside processing includes forming sacrificial layers, creating access holes, and depositing contact materials independently from front-side transistor fabrication. This segmentation allows each process to be optimized separately, achieving 10nm precision without overwhelming complexity in a single monolithic process.
Solution Approach 2:
Sacrificial layers are deposited and patterned on the backside before front-side processing completes. Access holes are formed in advance through the substrate, and contact materials are prepared beforehand. These preliminary actions on the backside enable precise alignment and reduce variability when front-side and backside processes are integrated, achieving the required manufacturing precision.
2Productivity
If device dimensions are reduced to increase density, then productivity is improved, but reliability deteriorates due to increased variability
Solution Approach 1:
The patent employs asymmetric gate spacer configurations where source and drain spacers have different widths or materials. This asymmetry compensates for process variability by independently optimizing source and drain regions, allowing density increase while maintaining performance consistency through differential compensation of manufacturing variations.
Solution Approach 2:
Different materials and structures are applied to source and drain regions locally. The backside contact structures use differentiated designs for source versus drain, with varying depths, materials, or geometries. This local differentiation addresses variability by tailoring each region's properties to compensate for specific process challenges, maintaining reliability at high density.
3Ease of manufacture
If symmetric gate spacers are used, then ease of manufacture is maintained, but parasitic capacitance increases
Solution Approach 1:
The gate spacers are designed with asymmetric dimensions or materials on source versus drain sides. This asymmetry reduces parasitic capacitance by optimizing the spacing and material composition for each side's specific electrical requirements, while the overall fabrication remains relatively simple through standard deposition and etching processes adapted for asymmetric patterns.
4Object-generated harmful factors
If backside processing is implemented, then parasitic resistance is reduced, but device complexity increases
Solution Approach 1:
The patent moves contact formation to the backside dimension of the substrate, creating vertical access paths through the substrate thickness. This dimensional transition allows contact materials to be deposited and patterned on the opposite side from transistor fabrication, reducing parasitic resistance by shortening current paths while organizing the increased process complexity into a systematic two-sided fabrication approach.
Data Source
AI summary
Integrated circuit structures having asymmetric epitaxial source or drain arrangements are described. An integrated circuit structure includes a gate stack over a plurality of horizontally stacked nanowires. A first epitaxial source or drain structure is at a first end of the plurality of horizontally stacked nanowires. A first gate spacer laterally between the gate stack and the first epitaxial source or drain structure. A second epitaxial source or drain structure is at a second end of the plurality of horizontally stacked nanowires. A second gate spacer is laterally between the gate stack and the first epitaxial source or drain structure. The first gate spacer has a width less than the second gate spacer or the tips of the first epitaxial source or drain structure have a greater lateral width than the tips of the second epitaxial source or drain structure by an amount of 10% or greater, or both.