Asymmetric Source-Drain Structures for Semiconductor Device Matching
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Solution Overview
Problem
In the design of integrated circuits, there is a challenge in achieving consistent performance due to the complexities of matching behavior in advanced semiconductor devices with smaller feature sizes, leading to issues like device mismatch and electrical characterization variability.
Innovation Solution
The method involves a multi-step fabrication process including the formation of a substrate, metal and dielectric layers, patterning, and annealing processes to create a semiconductor device with a source/drain epitaxial layer and gate electrodes, which reduces device mismatch by optimizing the placement and structure of these components.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If feature size is reduced to advance technology, then device density and integration capability are improved, but device mismatch and electrical characterization variability worsen
Solution Approach 1:
The patent applies local quality by creating asymmetric source/drain structures with different doping concentrations and geometries on opposite sides of the channel. Specifically, one source/drain region has a first doping concentration while the other has a second doping concentration, and their widths are intentionally made different to compensate for channel length variations and achieve better device matching despite scaled dimensions
Solution Approach 2:
The patent changes multiple parameters simultaneously including doping concentrations, region widths, and depth profiles to optimize device performance. By adjusting these parameters locally in the source/drain regions, the invention compensates for variability introduced by reduced feature sizes and achieves improved device matching
2Productivity
If feature size is reduced to advance technology, then device density and integration capability are improved, but electrical characterization variability worsens
Solution Approach 1:
The patent introduces local quality variations in the source/drain regions through asymmetric doping and geometry to compensate for electrical variability. The different doping concentrations and widths are specifically designed to stabilize electrical characteristics and reduce mismatch in scaled devices
Solution Approach 2:
The patent performs preliminary doping and structural formation of source/drain regions before final device fabrication steps. This preliminary action establishes optimized electrical characteristics early in the process, preventing variability from propagating through subsequent fabrication steps
3Manufacturing precision
If asymmetric source/drain structures are formed with different doping concentrations, then device mismatch is reduced, but fabrication process complexity increases
Solution Approach 1:
The patent segments the source and drain regions into distinct structures with different properties. By dividing the device into asymmetric source/drain components with specific doping concentrations and geometries, the invention achieves better device matching while managing fabrication complexity through modular process design
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the consistency and performance of semiconductor devices by reducing device mismatch and electrical characterization variability, improving the reliability of transistors such as PMOS and FinFETs.
Implementation Method 1
an annealing process is performed in an atmosphere of a gas including 50 vol % to 100 vol % of hydrogen to remove extra charges
Data Source
AI summary
A semiconductor device includes a first gate stack structure over a substrate, a source/drain epitaxial layer, a lightly doped region, and a silicide region. The source/drain epitaxial layer is disposed in the substrate and adjacent to the first gate stack structure. The lightly doped region is located in the substrate to be electrically connected to the source/drain epitaxial layer. The lightly doped region includes a first portion protrudes from a sidewall of the source/drain epitaxial layer. The silicide region is in contact with a top surface and sidewalls of a top portion of the source/drain epitaxial layer and a top surface of the first portion of the lightly doped region. The top portion of the source/drain epitaxial layer is higher than the top surface of the first portion of the lightly doped region.