Asymmetric Source/Drain Structure for Low-Capacitance Nanotransistors
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Solution Overview
Problem
Nanostructure transistor devices face challenges with dislocation defects in source/drain structures, which reduce device current and performance due to strain relaxation and increased parasitic capacitance, while eliminating these defects without inner spacers worsens parasitic capacitance and performance.
Innovation Solution
An asymmetric source/drain design is implemented, where an inner spacer structure is used on the drain side to reduce parasitic capacitance and an epitaxial layer is used on the source side to reduce dislocation defects, thereby improving strain and current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If inner spacer structures are used on both source and drain sides, then parasitic capacitance is reduced, but dislocation defects increase due to strain relaxation
Solution Approach 1:
The patent applies asymmetry by implementing inner spacer structures only on the drain side while using epitaxial growth on the source side without inner spacers. This asymmetric configuration allows the drain side to benefit from reduced parasitic capacitance through the inner spacer, while the source side maintains low dislocation defects through epitaxial growth, thereby resolving the technical contradiction between reducing parasitic capacitance and preventing dislocation defects
Solution Approach 2:
The patent applies local quality by tailoring the structure to different locations: inner spacers are placed only where needed (drain side) to reduce parasitic capacitance, while the source side uses epitaxial growth to minimize dislocation defects. This location-specific structural optimization allows each side to have the quality most suitable for its functional requirements, resolving the contradiction between the two opposing effects
2Reliability
If inner spacer structures are eliminated to reduce dislocation defects, then strain is improved, but parasitic capacitance increases and performance worsens
Solution Approach 1:
The asymmetric design allows the source side to eliminate inner spacers for reduced dislocation defects while the drain side retains inner spacers for reduced parasitic capacitance, thus resolving the contradiction by applying different solutions to different locations based on their specific requirements
Solution Approach 2:
The patent applies local quality by providing different structural treatments to the source and drain sides: the source side receives epitaxial growth without inner spacers to minimize dislocation defects, while the drain side receives inner spacer structures to minimize parasitic capacitance, thereby optimizing each side for its specific functional needs
3Ease of manufacture
If symmetric source/drain structures are used, then manufacturing is simplified, but performance is suboptimal due to inability to address different source/drain requirements
Solution Approach 1:
The patent transitions from symmetric to asymmetric source/drain design, where the drain side includes inner spacer structures and the source side uses epitaxial growth without inner spacers. This asymmetric configuration optimizes device performance by addressing the different requirements of source and drain sides, while the manufacturing process remains relatively straightforward by using sequential formation steps
Solution Approach 2:
The patent segments the source and drain structures into different configurations: the drain side is segmented with inner spacer structures to reduce parasitic capacitance, while the source side is segmented with epitaxial growth to reduce dislocation defects. This segmentation allows each side to be optimized independently for its specific functional requirements, improving overall device performance
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design reduces dislocation defects by 50-80%, lowers S/D resistance, and enhances device current, improving performance by 5-20% for p-type and 0.5-5% for n-type nanostructure transistors.
Implementation Method 1
an epitaxial layer is used on the source side to reduce dislocation defects
Data Source
AI summary
The present disclosure describes a semiconductor device having an asymmetric source/drain (S/D) design. The semiconductor device includes multiple semiconductor layers on a substrate, a gate structure wrapped around the multiple semiconductor layers, an inner spacer structure between the multiple semiconductor layers and in contact with a first side of the gate structure, and an epitaxial layer in contact with a second side of the gate structure. The second side is opposite to the first side.