Asymmetric Source Drain Diffusion for NVSRAM Reliability
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Solution Overview
Problem
Conventional nonvolatile static random access memory (NVSRAM) cells suffer from dynamic write inhibit (DWI) disturb, which leads to insufficient threshold voltage difference between SONOS transistors, making them unsuitable for reliable data retention and endurance, especially as transistor sizes and threshold voltages decrease.
Innovation Solution
The implementation of nonvolatile memory cells with programmable transistors featuring asymmetric source/drain (S/D) diffusion regions, where the S/D diffusion regions shared by recall transistors have a more graded p-n junction than those shared by store transistors, reducing gate-induced drain leakage (GIDL) and thereby mitigating DWI disturb.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional NVSRAM cell design with symmetric S/D diffusion regions is used, then manufacturing is simpler, but DWI disturb increases causing insufficient threshold voltage difference
Solution Approach 1:
The patent applies asymmetry by configuring the first S/D diffusion region with a first doping concentration and the second S/D diffusion region with a second doping concentration that differs from the first. This asymmetric doping structure creates different electrical characteristics in the recall and store transistors, reducing DWI disturb and ensuring sufficient threshold voltage difference for reliable data retention.
Solution Approach 2:
The patent implements local quality by applying different doping concentrations to specific S/D diffusion regions based on their functional requirements. The first S/D diffusion region (associated with recall transistor) has a different doping concentration than the second S/D diffusion region (associated with store transistor), optimizing local electrical properties to minimize DWI disturb while maintaining overall cell functionality.
2Quantity of substance
If transistor sizes decrease to increase density, then storage capacity improves, but DWI disturb becomes more severe
Solution Approach 1:
The patent changes the doping concentration parameter of S/D diffusion regions to compensate for DWI disturb effects that become more severe at smaller transistor sizes. By optimizing the doping concentrations in the first and second S/D diffusion regions, the patent maintains sufficient threshold voltage difference and data retention reliability even as transistor dimensions are reduced to increase memory density.
3Reliability
If LDD dose is reduced to lower DWI disturb, then threshold voltage stability improves, but manufacturing precision requirements increase
Solution Approach 1:
The patent applies local quality by implementing different doping concentrations in different S/D diffusion regions. The first S/D diffusion region has a first doping concentration optimized for recall transistor operation, while the second S/D diffusion region has a second doping concentration optimized for store transistor operation. This localized optimization achieves threshold voltage stability without requiring uniform LDD dose reduction across all transistors, thereby reducing manufacturing precision requirements.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces DWI disturb, enhancing the reliability of NVSRAM cells by maintaining a sufficient threshold voltage difference between transistors, thus improving data retention and endurance.
Implementation Method 1
reducing gate-induced drain leakage (GIDL) and thereby mitigating DWI disturb
Data Source
AI summary
A memory cell can include at least a first programmable section coupled between a supply node and a first data node; a volatile storage circuit coupled to the first data node; and the programmable section includes a programmable transistor having a first source/drain (S/D) region shared with a first transistor, and a second S/D region shared with a second transistor; wherein the first S/D region has a different dopant diffusion profile than the second S/D region, and the programmable transistor has a charge storage structure formed between its control gate and its channel. Methods of forming such a memory cell are also disclosed.