Asymmetric Source-Drain Angles for Semiconductor Bridging
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Solution Overview
Problem
As integration density in semiconductor devices increases, there is a risk of bridge or short issues between adjacent PMOS and NMOS transistors due to the proximity of their source/drain patterns, which can lead to reliability and performance concerns.
Innovation Solution
The semiconductor device design includes source/drain patterns with specific angled configurations, where the first angle θ1 is greater than the second angle θ2, allowing for a smaller width in one direction to reduce the risk of bridging between different types of transistors, and varying sizes of source/drain patterns to maintain performance and integration density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If source/drain patterns are placed close together to increase integration density, then productivity is improved, but reliability deteriorates due to bridge or short issues between adjacent transistors
Solution Approach 1:
The source/drain pattern is designed with an asymmetric angled configuration where the first angle is greater than the second angle. This asymmetry creates an optimized width profile that reduces the risk of bridging between adjacent transistors while maintaining high integration density, directly resolving the contradiction between productivity and reliability
Solution Approach 2:
The patent applies parameter changes by varying the angles of the source/drain pattern sides relative to the substrate surface. By optimizing these angular parameters, the pattern achieves a narrower effective width in critical directions, reducing short-circuit risk while preserving integration density
2Reliability
If source/drain pattern width is reduced to prevent bridging, then reliability is improved, but manufacturing precision becomes more difficult to control
Solution Approach 1:
By changing the angular parameters of the source/drain pattern rather than simply reducing width, the design achieves reliable spacing between adjacent transistors while maintaining manufacturing controllability. The angled configuration provides a balanced solution that satisfies both reliability and manufacturing precision requirements
Data Source
AI summary
A semiconductor device includes a first active fin protruding from a substrate, a first gate pattern covering a side surface and a top surface of the first active fin, and first source/drain patterns at opposite sides of the first gate pattern, each of the first source/drain patterns including a first lower side and a second lower side spaced apart from each other, a first upper side extended from the first lower side, a second upper side extended from the second lower side. The first lower side may be inclined at a first angle relative to a top surface of the substrate, the second upper side may be inclined at a second angle relative to the top surface of the substrate, and the first angle may be greater than the second angle.