Asymmetric Source/Drain Structure for Low-Defect Nanostructure Transistors

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Solution Overview

Problem

Nanostructure transistor devices face challenges with dislocation defects in source/drain structures, which affect strain on channels, device current, and parasitic capacitance, leading to degraded performance.

Innovation Solution

An asymmetric source/drain design is implemented in nanostructure transistors, featuring an inner spacer structure on one side and an epitaxial layer on the other, reducing dislocation defects and parasitic capacitance while improving strain and device current.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a conventional symmetric source/drain design is used in nanostructure transistors, then the manufacturing process is simpler, but dislocation defects occur frequently and device performance is degraded

Engineering Contradiction:

Improvedevice performanceVSAvoidsource/drain structure complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies asymmetry by implementing different structures on the source and drain sides of the nanostructure transistor. Specifically, one side features an inner spacer structure while the other side has an epitaxial layer, creating asymmetric source/drain regions that reduce dislocation defects and improve device performance by 5% to 20% for p-type transistors and 0.5% to 5% for n-type transistors.

Inventive Principle:

Principle #4Asymmetry

2Productivity

If the source/drain structure is simplified, then manufacturing is easier, but parasitic capacitance increases and device current decreases

Engineering Contradiction:

Improvedevice currentVSAvoidsource/drain structure complexity

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

The patent applies local quality by providing different structural treatments to different regions of the source/drain structure. The inner spacer structure is placed on one side to reduce parasitic capacitance, while the epitaxial layer is placed on the other side to reduce dislocation defects and improve carrier mobility, allowing each region to optimize for its specific function.

Inventive Principle:

Principle #3Local quality

3Reliability

If dislocation defects are reduced through better material quality, then strain on channels improves, but manufacturing precision requirements increase

Engineering Contradiction:

Improvestrain on channelsVSAvoidepitaxial layer precision

Core Design Contradiction:

ReliabilityVSManufacturing precision

Solution Approach 1:

The patent applies preliminary action by forming the inner spacer structure and epitaxial layer before final device operation. The inner spacer structure is created to pre-establish a defect-reduced region, and the epitaxial layer is grown in advance with controlled orientation to pre-establish low dislocation density, thereby improving strain on channels while managing manufacturing precision requirements.

Inventive Principle:

Principle #10Preliminary action

Data Source

PatentUS20250359229A1Semiconductor devices with asymmetric source/drain design

Publication Date: 2025.11.20 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

The present disclosure describes a semiconductor device having an asymmetric source/drain (S/D) design. The semiconductor device includes multiple semiconductor layers on a substrate, a gate structure wrapped around the multiple semiconductor layers, an inner spacer structure between the multiple semiconductor layers and in contact with a first side of the gate structure, and an epitaxial layer in contact with a second side of the gate structure. The second side is opposite to the first side.