Asymmetric Source and Drain Vias for Semiconductor Contact Resistance
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Solution Overview
Problem
Conventional methods for forming via structures in semiconductor devices are not amenable to creating asymmetric via structures, which are necessary to reduce contact resistances and improve device performance as semiconductor fabrication progresses to smaller technology nodes, as they do not allow independent adjustment of via sizes on the source and drain sides, leading to potential increases in chip footprint.
Innovation Solution
The solution decouples the fabrication of via structures on the source and drain sides, allowing for larger via structures on the source side to increase contact surface area and reduce contact resistance, while maintaining a smaller footprint by optimizing the dimensions and profiles of via trenches and structures to maximize interface areas.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional symmetric via structures are used, then manufacturing process is simple, but contact resistance is high and device performance deteriorates
Solution Approach 1:
The patent applies asymmetry by forming via structures with different dimensions on the source and drain sides of the semiconductor device. The first via structure has a first dimension that differs from a second dimension of the second via structure, allowing optimization of contact resistance independently on each side while maintaining asymmetric geometry to resolve the technical contradiction between reliability and device complexity.
Solution Approach 2:
The patent applies local quality by allowing different via structures to have different properties tailored to their specific locations. The source side via and drain side via can have different dimensions, materials, or configurations optimized for their respective electrical and mechanical requirements, thereby reducing contact resistance locally without requiring complete structural redesign.
2Reliability
If via size is increased to reduce contact resistance, then contact surface area increases, but chip footprint increases
Solution Approach 1:
The patent applies local quality by allowing different via structures to have different dimensions optimized for their specific locations. The source side via and drain side via can have different dimensions, materials, or configurations optimized for their respective electrical and mechanical requirements, thereby reducing contact resistance locally without requiring complete structural redesign.
Solution Approach 2:
The patent applies segmentation by dividing the via structure formation into separate, independent processes for the source side and drain side. This allows the first via structure and second via structure to be formed with different dimensions and properties, enabling independent optimization of contact resistance and footprint for each side of the device.
Data Source
AI summary
An exemplary semiconductor device includes a source feature and a drain feature disposed over a substrate. The semiconductor device further includes a source via electrically coupled to the source feature, and a drain via electrically coupled to the drain feature. The source via has a first size; the drain via has a second size; and the first size is greater than the second size. The semiconductor device may further include a first metal line electrically coupled to the source via and a second metal line electrically coupled to the drain via. The source via has a first dimension matching a dimension of the first metal line, and the drain via has a second dimension matching a dimension of the second metal line. The first metal line may be wider than the second metal line.