Asymmetric Spacer Layout for Dense Semiconductor Chip Stacks
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Solution Overview
Problem
The challenge in the semiconductor industry is to increase the integration density of semiconductor packages while maintaining efficiency in a limited package area, as the size and number of semiconductor chips within the package have increased.
Innovation Solution
The proposed semiconductor package design includes a substrate with two spacers, each supporting a semiconductor chip stack. A mold layer covers the chip stacks and spacers, ensuring direct contact and integration. The spacers have different widths and thicknesses, allowing for asymmetric structures that enhance integration density without overlapping the chip stacks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If semiconductor chips are increased in size and number within the package, then the degree of integration is improved, but the package area becomes more limited and crowded
Solution Approach 1:
The patent transitions from a two-dimensional planar arrangement of semiconductor chips to a three-dimensional stacked configuration. Multiple chip stacks are arranged vertically along the third direction, allowing more chips to be integrated within the same footprint area on the substrate. This vertical stacking approach resolves the contradiction by utilizing the Z-axis dimension to increase chip quantity without expanding the package's horizontal footprint.
Solution Approach 2:
The patent implements a nested structure where multiple semiconductor chips are stacked within vertical columns, with each chip positioned above the previous one in the third direction. These chip stacks are then nested within the overall package structure, surrounded by mold layers and supported by spacers. This nesting arrangement maximizes the number of chips that can be contained within the limited package volume.
2Stability of the object's composition
If spacers are used to support semiconductor chip stacks, then structural stability is improved, but the device complexity increases due to additional components
Solution Approach 1:
The spacers in the patent serve multiple functions simultaneously: they provide mechanical support for the semiconductor chip stacks, maintain proper spacing between adjacent stacks to prevent interference, and facilitate the molding process by defining the boundaries for mold layer placement. This multi-functionality reduces the need for additional separate components, thereby limiting the increase in device complexity while achieving structural stability.
3Area of moving object
If asymmetric spacer widths are used, then space utilization is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent employs asymmetric spacer designs where the first spacer has a different width in the first direction compared to the width of the second spacer. This asymmetry is deliberately introduced to optimize space utilization within the package, allowing chip stacks of different sizes or configurations to be accommodated efficiently. The asymmetric design enables better packing density while the patent addresses the manufacturing challenge through precise definition of the asymmetric dimensions in the design specifications.
Data Source
AI summary
A semiconductor package includes a substrate extending in first and second directions crossing each other. A first spacer is on the substrate. A first semiconductor chip stack is on the first spacer and includes semiconductor chips stacked in a third direction. A second spacer is disposed on the substrate and is spaced apart from the first spacer in the first direction. A second semiconductor chip stack is on the second spacer and includes semiconductor chips stacked in the third direction. A mold layer integrally covers the first and second semiconductor chip stacks and directly contacts side surfaces of the first and second spacers. The first and second semiconductor chip stacks are spaced apart from each other in the first direction. A width of the first spacer in the first direction is greater than a width of the second spacer in the first direction.