Asymmetric SRAM Cell Using Dual Stress Liner
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Solution Overview
Problem
As semiconductor technology advances, the miniaturization of SRAM cells leads to increased variability in transistor electrical characteristics, causing read and write failures due to sensitivity to device variability, making it challenging to maintain both cell stability and write margin, especially in sub-micron feature sizes.
Innovation Solution
Implementing asymmetric construction of SRAM cells using dual stress liner (DSL) technology, where compressive nitride liners are applied to p-channel MOS transistors and tensile nitride liners to n-channel MOS transistors, enhancing carrier mobility and improving static noise margin without increasing chip area or manufacturing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If symmetric SRAM cell construction is used, then manufacturing simplicity is maintained, but device variability causes read and write failures
Solution Approach 1:
The patent applies asymmetry by intentionally designing the SRAM cell with mismatched transistor parameters. Specifically, the pass-gate transistors are made stronger relative to the driver transistors, and the load transistors are optimized independently on each side. This asymmetric construction compensates for process variability and improves both read and write margins without requiring additional transistors or cell area.
2Reliability
If pass-gate transistors are strengthened to improve write margin, then write functionality improves, but cell stability deteriorates
Solution Approach 1:
The patent applies local quality by optimizing different transistor types with different characteristics within the same cell. The pass-gate transistors are designed with higher drive strength (larger W/L ratio) to improve write margin, while the driver transistors are optimized for stability. The load transistors are independently optimized on each side to balance the cell. This localized optimization allows each transistor to perform its specific function at peak efficiency without compromising overall cell stability.
3Productivity
If device feature sizes are reduced for miniaturization, then memory capacity increases, but device variability increases causing functional failures
Solution Approach 1:
The patent applies parameter changes by systematically adjusting transistor design parameters (W/L ratios, threshold voltages, channel widths) to compensate for scaling effects. As feature sizes are reduced, the pass-gate transistors are made proportionally larger or given higher mobility enhancement to maintain adequate drive strength. The driver transistors are optimized for stability with appropriate sizing. These parameter adjustments are made while maintaining the same physical cell area, thus improving reliability without sacrificing memory capacity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances static noise margin and cell stability in SRAM cells, allowing for stronger pass-gate transistors to improve write margin without compromising stability, all while maintaining compatibility with CMOS technology and modern sub-micron transistor sizes, and without additional chip area or manufacturing costs.
Implementation Method 1
compressive nitride liners are applied to p-channel MOS transistors and tensile nitride liners to n-channel MOS transistors, enhancing carrier mobility
Implementation Method 2
compressive nitride liners are applied to p-channel MOS transistors and tensile nitride liners to n-channel MOS transistors, enhancing carrier mobility
Data Source
AI summary
A solid-state memory in which each memory cell is constructed of complementary metal-oxide-semiconductor (CMOS) inverters implemented with dual stress liner (DSL) technology. Asymmetry is incorporated into each memory cell by constructing one of the inverter transistors or the pass-gate transistor using the stress liner with opposite stress characteristics from its opposing counterpart. For example, both of the p-channel load transistors and one of the n-channel driver transistors in each memory cell may be constructed with a compressive nitride liner layer while the other driver transistor is constructed with a tensile nitride liner layer. In another implementation, one of the n-channel pass-gate transistors is constructed with a compressive nitride liner layer while the other pass-gate transistor is constructed with a tensile nitride liner layer. Improved cell stability due to the resulting asymmetric behavior is implemented in a cost-free manner.