Asymmetric SOI SRAM Cell Floating Body Mitigation
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Solution Overview
Problem
The floating body effect in Silicon-on-Insulator (SOI) SRAM circuits leads to variability issues, degrading stability and performance due to parasitic transistors and increased current consumption, which existing solutions often address at the cost of device area and complexity.
Innovation Solution
Implementing asymmetric transistors with selective halo implants, particularly on the source side, to reduce the floating body potential and variability, without the need for body tie formation or complex integration, using masking and photolithography techniques to achieve asymmetry and lower parasitic resistances.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If body tie structures are employed in SOI CMOS to add a contact to the floating body node, then the floating body effect is mitigated, but parasitic resistances and capacitances are introduced as well as significant area penalties
Solution Approach 1:
The patent employs asymmetric transistor design where one transistor in the pull-up or pull-down pair has a different threshold voltage than its counterpart. This is achieved through selective halo implantation on one side of the transistor channel, creating an asymmetric doping profile. The asymmetric threshold voltage compensates for floating body effects without requiring additional body contact structures, thereby avoiding parasitic resistances and capacitances associated with traditional body tie structures.
2Reliability
If the linear threshold voltage (Vt) of the FETs in the array is increased to address floating body variability, then stability is improved, but the overall array performance is lowered
Solution Approach 1:
The patent applies selective halo implantation to create different threshold voltages in specific transistors within the SRAM cell. Rather than uniformly increasing the threshold voltage of all FETs in the array, the asymmetric implantation is applied locally to specific pull-up or pull-down transistors. This localized modification addresses floating body variability in critical transistors while preserving the performance characteristics of other transistors, thus maintaining overall array performance.
3Reliability
If asymmetric transistors with selective halo implants are implemented, then floating body variability is reduced, but device fabrication complexity increases
Solution Approach 1:
The asymmetric halo implantation is integrated into the existing CMOS fabrication process flow as a preliminary step during transistor formation. The selective implantation is performed during the standard manufacturing sequence, utilizing existing masking and doping infrastructure. By incorporating the asymmetric implantation early in the fabrication process rather than as a separate post-processing step, the patent minimizes additional fabrication complexity while achieving the desired threshold voltage asymmetry.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively mitigates the floating body effect, reducing variability and maintaining performance by limiting the floating body voltage and minimizing parasitic capacitances, thus enhancing the stability and yield of SRAM cells.
Implementation Method 1
Implementing asymmetric transistors with selective halo implants, particularly on the source side, to reduce the floating body potential and variability
Implementation Method 2
The transistor's body forms a capacitor against the insulated substrate. The charge accumulates on this capacitor and may cause adverse effects
Data Source
AI summary
A memory cell having N transistors including at least one pair of access transistors, one pair of pull-down transistors, and one pair of pull-up transistors to form a memory cell, wherein N is an integer at least equal to six, wherein each of the access transistors and each of the pull-down transistors is a same one of an n-type or a p-type transistor, and each of the pull-up transistors is the other of an n-type or a p-type transistor, wherein at least one of the pair of the pull down transistors and the pair of the pull up transistors are asymmetric.