Asymmetric SRAM Cell Split Transistors Write Stability
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Solution Overview
Problem
Existing SRAM cell designs face challenges in data transfer efficiency during write operations and data integrity during read operations, particularly due to limitations in on-state current and threshold voltage of transistors, leading to issues like write failures and data upsets.
Innovation Solution
Incorporating auxiliary driver and load transistors with adjusted dimensions and fabrication processes to provide higher on-state current and improved threshold voltages, connected to power supply nodes during specific operations to enhance data transfer and reduce data inversion and leakage current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional SRAM cell designs are used, then device complexity is low, but data transfer efficiency during write operations deteriorates due to limitations in on-state current and threshold voltage
Solution Approach 1:
The driver transistor is segmented into two separate transistors (first driver transistor and second driver transistor) that operate in parallel. This segmentation allows each transistor to contribute to the total drive current, effectively doubling the on-state current capability and improving data transfer efficiency during write operations without requiring a single oversized transistor.
Solution Approach 2:
The patent employs asymmetric transistor sizing where the first driver transistor has different dimensions (width and/or length) than the second driver transistor. This asymmetry allows optimization of the strong side of the SRAM cell to provide higher drive strength for write operations while maintaining appropriate threshold voltages, resolving the contradiction between current drive capability and threshold voltage control.
2Power
If transistor dimensions are increased to provide higher on-state current, then data transfer efficiency improves, but leakage current increases leading to data upsets
Solution Approach 1:
Different transistors within the SRAM cell are assigned different dimensions and characteristics based on their specific functional requirements. The driver transistors are optimized for high on-state current with larger dimensions, while the load transistors and passgate transistors are sized to minimize leakage. This local quality differentiation allows the cell to achieve high drive strength without proportionally increasing leakage current across all transistors.
Solution Approach 2:
The patent utilizes different threshold voltage parameters for different transistors in the cell. By selecting transistors with appropriate threshold voltages (e.g., higher threshold voltage for load transistors to reduce leakage, optimized threshold voltage for driver transistors to balance drive current and leakage), the design achieves high on-state current capability while controlling leakage-induced data upsets.
3Reliability
If symmetric transistor configuration is used, then manufacturing simplicity is maintained, but write failures occur due to insufficient drive strength on the strong side
Solution Approach 1:
The patent deliberately introduces asymmetry by providing a first driver transistor and a second driver transistor with different dimensions on the strong side of the SRAM cell. This asymmetric configuration provides enhanced drive strength to overcome the inherent weakness in conventional symmetric designs, eliminating write failures caused by insufficient drive capability while maintaining overall cell functionality.
Solution Approach 2:
By segmenting the driver function into multiple transistors working in parallel, the patent achieves cumulative drive strength that exceeds what a single symmetric transistor could provide. This segmentation approach ensures reliable write operations by distributing the drive current requirement across multiple devices, each contributing to the overall write capability.
4Reliability
If auxiliary driver and load transistors are added, then data integrity during read operations improves, but device complexity and area increase
Solution Approach 1:
The first and second driver transistors serve multiple functions: they provide enhanced drive current for write operations, contribute to read stability through their parallel configuration, and help maintain data integrity during standby. This multi-functionality allows the patent to improve reliability without adding dedicated auxiliary transistors that would further increase area.
Solution Approach 2:
The patent merges the functions of driving, loading, and data retention into a compact configuration where the first and second driver transistors work in conjunction with the load transistors and passgate transistors. This merging of functions into a coordinated transistor network achieves improved data integrity while minimizing the area overhead compared to adding separate auxiliary transistors for each function.
Data Source
AI summary
An integrated circuit containing an SRAM cell array in which each SRAM cell includes an auxiliary NMOS driver or PMOS load transistor plus a bit-side passgate transistor and a bit-bar-side passgate transistor. An integrated circuit containing an SRAM cell array in which each SRAM cell includes an auxiliary PMOS driver or NMOS load transistor plus a bit-side passgate transistor and a bit-bar-side passgate transistor. A process of operating an integrated circuit containing an SRAM cell array in which each SRAM cell includes an auxiliary NMOS driver or PMOS load transistor plus a bit-side passgate transistor and a bit-bar-side passgate transistor. A process of operating an integrated circuit containing an SRAM cell array in which each SRAM cell includes an auxiliary PMOS driver or NMOS load transistor plus a bit-side passgate transistor and a bit-bar-side passgate transistor.