Asymmetric Storage Node Contacts for DRAM Alignment Tolerance
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional methods for forming storage node contact structures in semiconductor devices, such as DRAM, involve complex techniques and separate landing pads, leading to increased manufacturing costs and reduced production yield due to misalignment and instability in connections between storage node contact structures and storage structures.
Innovation Solution
The implementation of asymmetric storage node contact structures with larger top portions serving as landing pads, allowing for reliable connections and eliminating the need for separate landing pads, thereby simplifying the manufacturing process and reducing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional methods use separate landing pads for storage node contact structures, then connection stability is improved, but device complexity and manufacturing cost increase
Solution Approach 1:
The patent merges the storage node contact structure and landing pad into a single integrated structure. The contact structure includes a first portion contacting the storage node and a second portion serving as the landing pad, eliminating the need for separate landing pads while maintaining connection stability and reducing manufacturing complexity
2Ease of manufacture
If conventional methods use symmetric contact structures, then manufacturing is simplified, but connection reliability and alignment tolerance are reduced
Solution Approach 1:
The patent employs an asymmetric contact structure where the top view shows different dimensions in the first direction versus the second direction. The first portion has a first dimension in the first direction and a second dimension in the second direction, with the ratio between these dimensions optimized for both manufacturing ease and connection reliability. This asymmetric design provides better alignment tolerance and connection reliability while remaining manufacturable
3Productivity
If contact structures are scaled down for smaller process sizes, then productivity is improved, but manufacturing precision and alignment accuracy deteriorate
Solution Approach 1:
The patent optimizes the dimensional parameters of the contact structure, specifically the ratio between the first dimension (in the first direction) and second dimension (in the second direction). By controlling this ratio within a specific range, the structure maintains adequate alignment tolerance and manufacturing precision even when scaled down to smaller process sizes, thereby enabling productivity improvement without sacrificing precision
Data Source
AI summary
The present disclosure relates to storage node contact structures in semiconductor devices and fabrication methods thereof. An example semiconductor device includes an array of memory cells. The array of memory cells includes a first row of memory cells arranged along a first direction. At least one memory cell of the first row of memory cells includes a first vertical transistor, a first storage node contact structure, and a first storage structure that are stacked along a second direction perpendicular to the first direction. The first storage node contact structure includes a first top portion in contact with the first storage structure and a first bottom portion in contact with the first vertical transistor. A first top cross section of the first top portion is asymmetric.