Asymmetric Strained Source-Drain Fin Transistors
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Solution Overview
Problem
Conventional transistors do not achieve optimal strain in the channel region, which limits their performance.
Innovation Solution
The transistor structure includes fin regions with asymmetrically strained source/drain portions and a channel region, where SiGe or SiC material is epitaxially grown on exposed surfaces of the fin region to create strain in the channel, ensuring that no surface of the source/drain portions is in direct contact with the strain creating material.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If SiGe or SiC is epitaxially grown on source/drain portions of the fin region to provide strain, then strain is introduced into the channel region, but the resulting structure does not have optimal strain in the channel region
Solution Approach 1:
The patent applies local quality by creating asymmetric strain in the channel region through selective epitaxial growth of SiGe or SiC on only one source/drain portion (either source or drain) rather than both. This localized approach optimizes the strain distribution specifically in the channel region adjacent to the selectively modified source/drain portion, achieving better carrier mobility enhancement without unnecessary complexity in other regions.
Solution Approach 2:
The patent implements asymmetry by intentionally creating non-uniform strain distribution in the channel region through asymmetric source/drain structures. One source/drain portion has different composition (higher Ge or C content) compared to the other, generating asymmetric strain fields that are optimized for carrier transport in the channel, thereby improving transistor performance beyond symmetric conventional structures.
2Manufacturing precision
If conventional symmetric source/drain structures are used, then manufacturing is simpler, but the channel region does not achieve higher strain
Solution Approach 1:
The patent applies local quality by creating asymmetric strain in the channel region through selective epitaxial growth of SiGe or SiC on only one source/drain portion (either source or drain) rather than both. This localized approach optimizes the strain distribution specifically in the channel region adjacent to the selectively modified source/drain portion, achieving better carrier mobility enhancement without unnecessary complexity in other regions.
Solution Approach 2:
The patent changes material composition parameters by varying the Ge or C content in the epitaxially grown SiGe or SiC layer on the selected source/drain portion. By adjusting these compositional parameters, the strain magnitude in the channel region can be precisely controlled and optimized, achieving the desired strain level without requiring complex structural modifications throughout the entire device.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enhances the strain in the channel region, thereby improving the operation of the transistor by aligning the crystal lattice mismatch between the strain creating regions and the channel, leading to better performance.
Implementation Method 1
SiGe (silicon-germanium) or SiC (silicon-carbon) is epitaxially grown on source/drain portions of the fin region
Implementation Method 2
aligning the crystal lattice mismatch between the strain creating regions and the channel, leading to better performance
Data Source
AI summary
A semiconductor structure. The structure includes (a) a fin region having (i) a first source/drain portion having a first surface and a third surface, wherein the first and third surfaces are (A) parallel to each other and (B) not coplanar, (ii) a second source/drain portion having a second surface and a fourth surface, wherein the second and fourth surfaces are (A) parallel to each other and (B) not coplanar, and (iii) a channel region; (b) a gate dielectric layer; (c) a gate electrode region, wherein the gate dielectric layer (i) is sandwiched between, and (ii) electrically insulates the gate electrode region and the channel region; and (d) first second strain creating regions on the third and fourth surfaces, respectively, wherein the first and second strain creating regions comprise a strain creating material.