Asymmetric Strained Source/Drain for Drive Current and Leakage
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Solution Overview
Problem
Conventional field effect transistors face a design challenge in optimizing both drive current and junction leakage, as the size of semiconductor components shrinks, requiring a trade-off between these characteristics.
Innovation Solution
The implementation of an asymmetric strained source/drain structure in field effect transistors, achieved through a method involving dry and wet etching processes, stress-inducing layer formation, and dislocation creation, which allows for optimized drive current and reduced junction leakage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If the source and drain regions are made smaller to increase drive current through higher stress, then drive current is improved, but junction leakage increases
Solution Approach 1:
The patent applies asymmetry by creating different stress conditions in the source and drain regions. The source region is subjected to higher stress through selective wet etching and stress-inducing layer formation, while the drain region maintains lower stress. This asymmetric stress distribution enables the source to provide high drive current while the drain prevents excessive junction leakage, resolving the technical contradiction between these two opposing requirements.
Solution Approach 2:
The patent implements local quality by applying different etching and stress-inducing treatments to specific regions. The first region (source) undergoes wet etching and stress-inducing layer formation to create localized high stress, while the second region (drain) is masked and protected from these treatments. This localized differentiation allows each region to be optimized for its specific function, enabling high drive current from the source while maintaining low junction leakage in the drain.
2Ease of manufacture
If a symmetrical source/drain structure is used for ease of manufacture, then manufacturing simplicity is improved, but device performance optimization deteriorates
Solution Approach 1:
The patent applies segmentation by dividing the source and drain fabrication into separate, independent processes. The first region is processed through wet etching and stress-inducing layer formation, while the second region is masked and protected. This segmentation allows each region to be independently optimized for its specific function, achieving both manufacturing feasibility and enhanced device performance through differentiated regional treatment.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach simultaneously enhances drive current and minimizes junction leakage, thereby improving the overall performance of field effect transistors by strategically inducing stress in the channel region and managing stress distribution across the source and drain regions.
Implementation Method 1
A stress-inducing layer is then formed in the widened first trench and in the second trench
Implementation Method 2
recrystallizing the amorphous layer, thereby forming a dislocation in the first region
Data Source
AI summary
A method of forming a semiconductor structure includes: providing a substrate including an upper surface, a gate structure disposed on the upper surface, a spacer disposed on a sidewall of the gate structure, a first region in the substrate, and a second region in the substrate; masking the second region and amorphizing the first region, such that an amorphous layer is formed in the first region; depositing a stress layer on the substrate, wherein the stress layer conformally covers the gate structure, the spacer, the first region and the second region; and recrystallizing the amorphous layer, thereby forming a dislocation in the first region.