Asymmetric Stressing Layers for SRAM Read-Write Margin
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Solution Overview
Problem
SRAM memories face challenges in reading/writing stability due to reduced operating voltages and increased threshold voltage variations in CMOS manufacturing processes, necessitating improved read and write margins.
Innovation Solution
The implementation of MOS transistors with asymmetric stressing layers, featuring grooves on both sides of the gate structure filled with stressing materials, where one groove has a sidewall perpendicular to the substrate and the other has a sidewall protruding toward the channel region, allowing for different source-drain saturation currents in different current directions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If process node is shrunk in CMOS manufacturing processes, then device integration density is improved, but reading/writing stability deteriorates due to reduced operating voltages and increased threshold voltage variations
Solution Approach 1:
The patent applies local quality by introducing asymmetric stressing layers with different configurations on opposite sides of the gate structure. One side has a stressing layer extending to the gate, while the other side has a different configuration, creating localized stress differences that selectively modulate carrier mobility in specific regions to improve read and write margins
Solution Approach 2:
The patent directly applies asymmetry by configuring stressing layers differently on opposite sides of the gate structure. The asymmetric stress distribution creates different effective channel lengths and carrier mobility characteristics on each side, enabling improved transistor performance for SRAM stability without requiring symmetric modifications
2Reliability
If asymmetric stressing layers are implemented with different groove configurations, then carrier mobility and stress distribution are optimized, but device structure complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the stress application into distinct segments - separate first and second grooves with different configurations on opposite sides of the gate. This segmented approach allows independent optimization of stress distribution on each side while maintaining manufacturability through standardized processing steps
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enhances both read and write margins of SRAM memory cells by optimizing carrier mobility and stress distribution, thereby improving stability and performance.
Implementation Method 1
a first groove having a sidewall perpendicular to the surface of the semiconductor substrate and a second groove having a sidewall protruding toward a channel region under the gate structure. Each of the first groove and the second groove can be filled with a stressing material
Data Source
AI summary
Various embodiments provide an MOS transistor, a formation method thereof, and an SRAM memory cell circuit. An exemplary MOS transistor can include a semiconductor substrate including a first groove on one side of a gate structure and a second groove on the other side of the gate structure. The first groove can have a sidewall perpendicular to a surface of the semiconductor substrate. The second groove can have a sidewall protruding toward a channel region under the gate structure. A stressing material can be disposed in the first groove to form a drain region and in the second groove to form a source region. Stress generated in the channel region of the MOS transistor can be asymmetric. The MOS transistor can be used as a transfer transistor in an SRAM memory cell circuit to increase both read and write margins of the SRAM memory.