Asymmetric Substrate Structure for Cost Reduction

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Solution Overview

Problem

The high cost of manufacturing circuit boards with ultrafine lines on both surfaces is a significant issue due to the need for two separate ultrafine line processes, which increases production expenses.

Innovation Solution

A substrate structure is manufactured with a patterned first metal layer, a patterned second metal layer, and through holes, where the first trace layer is embedded within a dielectric layer on one surface and the second trace layer is disposed on the surface of another dielectric layer on the opposite side, reducing overall thickness and manufacturing costs by minimizing the use of expensive ultrafine line processes.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If ultrafine line processes are performed on both surfaces to achieve circuit boards with ultrafine lines on top and bottom surfaces, then the circuit board quality and functionality are improved, but the manufacturing cost increases extremely

Engineering Contradiction:
Improveultrafine line precisionVSAvoidmanufacturing cost
Core Design Contradiction:
Manufacturing precisionVSEase of manufacture

Solution Approach 1:

The patent applies different line specifications to different surfaces: the first surface maintains ultrafine lines for high-precision circuits, while the second surface uses ordinary lines for grounding or bias functions. This local differentiation allows the circuit board to achieve high functionality where needed while reducing manufacturing costs in areas where ultrafine precision is not required.

Inventive Principle:
Principle #3Local quality

2Adaptability or versatility

If ultrafine line processes are performed on both surfaces, then the circuit board functionality is improved, but the number of processes increases

Engineering Contradiction:
Improvecircuit board functionalityVSAvoidnumber of processes
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent implements local quality by assigning different functional requirements to different surfaces: the first surface receives ultrafine line processing for high-frequency signal circuits, while the second surface receives ordinary line processing for grounding and DC bias circuits. This reduces the total number of ultrafine line processes from two to one, simplifying the manufacturing workflow while maintaining full circuit functionality.

Inventive Principle:
Principle #3Local quality

3Length of moving object

If the substrate thickness is reduced to achieve slimness, then the electronic product compactness is improved, but the manufacturing complexity increases

Engineering Contradiction:
Improvesubstrate thicknessVSAvoidmanufacturing complexity
Core Design Contradiction:
Length of moving objectVSDevice complexity

Solution Approach 1:

The patent employs asymmetric trace layer design where the first trace layer on the first surface uses ultrafine lines for high-precision circuits, while the second trace layer on the second surface uses ordinary lines for grounding and bias functions. This asymmetric approach allows thickness reduction while maintaining manufacturing feasibility, as not all layers require the same level of precision and complexity.

Inventive Principle:
Principle #4Asymmetry

Data Source

PatentUS8322032B2Substrate structure and method for manufacturing the same
Publication Date: 2012.12.04 ADVANCED SEMICON ENG INC
  • US8322032B2 patent drawing
  • US8322032B2 patent drawing
  • US8322032B2 patent drawing

AI summary

A method for manufacturing a substrate structure is provided. The method includes the following steps. A substrate is provided. The substrate has a patterned first metal layer, a pattern second metal layer and a through hole. After that, a first dielectric layer and a second dielectric layer are formed at a first surface and a second surface of the substrate, respectively. The second surface is opposite to the first surface. Then, the first dielectric layer and the second dielectric layer are patterned. After that, a first trace layer is formed at a surface of the patterned first dielectric layer. The first trace layer is embedded into the patterned first dielectric layer and is coplanar with the first dielectric layer. Then, a second trace layer is formed on a surface of the second dielectric layer.