Gate-All-Around Semiconductor Device Asymmetric Substrate Width
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Solution Overview
Problem
Conventional semiconductor devices with gate-all-around structures suffer from large parasitic capacitance and leakage due to poor control ability at the bottom of the gate, leading to suboptimal electrical performance.
Innovation Solution
A fabrication method involving the alternate stacking of sacrificial and liner layers on a substrate, followed by etching to form fins and reducing the substrate width at the bottom of the sacrificial layer, which enhances the control effect of the gate-all-around structure and reduces parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional gate-all-around structure is formed with uniform substrate width, then the gate structure can be easily fabricated, but the control ability at the bottom of the gate is poor resulting in large parasitic capacitance and leakage current
Solution Approach 1:
The substrate width is made asymmetric by reducing it at the bottom region beneath the gate-all-around structure. This creates a narrower substrate width at the bottom compared to the top, allowing the gate to exert stronger control over the channel at the critical bottom region where parasitic effects are most problematic, thereby reducing parasitic capacitance and leakage current.
Solution Approach 2:
The substrate is given different widths at different locations: a reduced width at the bottom region under the gate and a larger width at the sides. This local variation in substrate geometry optimizes the control ability specifically where needed (at the bottom) without unnecessarily increasing device area elsewhere, addressing the parasitic capacitance problem locally rather than globally.
2Reliability
If the substrate width at the bottom is reduced to enhance gate control, then parasitic capacitance and leakage are reduced, but the fabrication process becomes more complex
Solution Approach 1:
The substrate width reduction is performed as a preliminary step before forming the gate-all-around structure. By pre-shaping the substrate with the narrowed bottom region, subsequent gate fabrication steps can proceed with standard processes, avoiding the need for complex lithography or etching patterns that would be required if the asymmetric substrate shape were created after gate deposition.
Data Source
AI summary
The present disclosure provides a semiconductor device and a fabrication method. The method includes: providing a substrate; forming at least one sacrificial layer and at least one liner layer, that are alternately stacked over each other, on the substrate; etching the at least one liner layer and the at least one sacrificial layer until the substrate is exposed, to form a plurality of fins, discretely arranged on the substrate; and etching a portion of a thickness of the substrate, such that a width of the etched portion of the substrate at a bottom of the at least one sacrificial layer is less than a width of the at least one liner layer of the plurality of fins.