Semiconductor Package Layout for Compact High-Current Switching
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Solution Overview
Problem
Conventional semiconductor devices with two semiconductor elements of the same shape face difficulties in being used as switching elements for inverters or relays, especially when handling large currents, due to increased wiring area and width, making it challenging to achieve both functionality and size suppression.
Innovation Solution
A semiconductor device configuration with first and second semiconductor elements, each having two electrodes on two surfaces, connected to respective terminals with different area ratios, and a sealing resin covering these elements and terminals, allowing for mounting on a wiring board to function as switching elements while minimizing size increase.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional semiconductor devices with two semiconductor elements of the same shape are used, then the device structure is simple and easy to manufacture, but the wiring area and width increase when handling large currents, making it difficult to suppress device size
Solution Approach 1:
The patent applies asymmetry by configuring the two semiconductor elements with different shapes - one element has a larger area than the other. This asymmetric design allows the terminals to be arranged more efficiently, reducing the overall device area while maintaining the capability to handle large currents. The different element shapes enable optimized current distribution and reduced wiring requirements compared to symmetric configurations.
Solution Approach 2:
The patent utilizes dimensional optimization by arranging the semiconductor elements and terminals in a specific spatial configuration. The elements are positioned to share common terminals and wiring paths, effectively using the available space in multiple dimensions. This dimensional arrangement reduces the planar area required while maintaining electrical performance for large current handling.
2Power
If the semiconductor device is designed to handle large currents, then the current handling capability is improved, but the wiring area and width increase, making it challenging to maintain compactness
Solution Approach 1:
The patent applies merging by having the two semiconductor elements share common terminals and wiring paths. Instead of providing separate complete wiring for each element, the design combines the wiring structure so that currents from both elements can flow through shared external terminals. This merging of wiring paths significantly reduces the total wiring area and width while maintaining the ability to handle the combined large current from both elements.
3Area of stationary object
If the terminal widths and distances are reduced to maintain compactness, then the device size is suppressed, but the capability to handle large currents is compromised
Solution Approach 1:
The patent applies local quality by having different terminal and wiring configurations in different regions of the device. The semiconductor element with the larger area is positioned to handle the majority of the current load, while the smaller element provides supplementary current handling. The terminal widths and spacing are optimized locally according to the current distribution requirements, allowing compact overall dimensions while maintaining adequate current handling capability through localized optimization rather than uniform scaling.
Data Source
AI summary
A semiconductor device includes: first and second semiconductor elements each having two electrodes respectively disposed on two surfaces; two first terminals respectively connected to the two electrodes of the first semiconductor element and arranged side by side in one direction; two second terminals respectively connected to the two electrodes of the second semiconductor element, and arranged side by side in the one direction to be adjacent to the two first terminals; and a sealing resin portion covering the first and second semiconductor elements and the first and second terminals in a state where facing surfaces of the first and second terminals are exposed from the sealing resin portion. The facing surfaces of the two first terminals have different area ratios, the facing surfaces of the two second terminals have different area ratios, and one of the first terminals is arranged adjacent to both the two second terminals.