Asymmetric TFT Electrode Overlap Reduces Parasitic Capacitance
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Solution Overview
Problem
Liquid crystal display devices face delays in data voltage transmission due to parasitic capacitance, which affects charging time, especially under high-speed driving conditions.
Innovation Solution
The design includes a thin film transistor with a drain electrode that overlaps the gate electrode more than the source electrode, reducing parasitic capacitance between the source and gate electrodes while maintaining a sufficient channel width, thereby reducing data voltage delay and ensuring sufficient charging time for pixels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If the overlapping area between the gate electrode and the source electrode is increased to maintain sufficient channel width, then the transistor's current driving capability is improved, but the parasitic capacitance between the source electrode and gate electrode increases, causing data voltage delay
Solution Approach 1:
The patent applies local quality by creating asymmetric overlapping areas between the gate electrode and the source/drain electrodes. Specifically, the gate electrode overlaps with the drain electrode in a first direction while having minimal overlap with the source electrode in the same direction. This localized differentiation allows the channel to maintain sufficient width for good current driving capability while minimizing parasitic capacitance formation at the source-gate interface, thereby reducing data voltage delay.
2Speed
If the data line driving speed is increased to improve display response time, then the display's dynamic performance is improved, but the charging time for pixels becomes insufficient due to parasitic capacitance effects
Solution Approach 1:
The patent changes the geometric parameters of the electrode configuration by controlling the overlapping areas between the gate electrode and source/drain electrodes. By optimizing these dimensional parameters, the parasitic capacitance is minimized, which allows the data line to drive at higher speeds while still providing sufficient charging time for pixels. This parameter optimization enables the display to achieve fast response times without compromising pixel charging completion.
Data Source
AI summary
A display device which includes a substrate, a gate line formed on the substrate, a data line intersecting the gate line, and a thin film transistor having a gate electrode connected to the gate line, a source electrode which overlaps the gate electrode and is connected to the data line, and a drain electrode which overlaps the gate electrode. The overlapping area between the gate electrode and the drain electrode is larger than the overlapping area between the gate electrode and the source electrode.