Asymmetric-Threshold Transistor Structure for Buck Converter Dead Time
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Solution Overview
Problem
Buck converters experience voltage drops during dead periods, leading to current flow through body diodes, which increases interference with neighboring devices and reduces precision in power supply control, necessitating increased spacing between IC devices.
Innovation Solution
A transistor with an asymmetric threshold voltage is implemented, featuring a doping extension region that extends deeper under the gate structure than the lightly doped drain region, providing a conductive path for reverse current while maintaining high forward threshold voltage, thus minimizing current through the body diode during dead periods.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional transistor is used in a buck converter, then the device can operate during dead periods, but voltage drops cause current to flow through the body diode, increasing interference with neighboring devices
Solution Approach 1:
The transistor is designed with asymmetric doping concentrations in the channel region: a first doping concentration in a first portion and a second doping concentration in a second portion, where the concentrations differ. This asymmetry creates different threshold voltages for forward and reverse conduction, allowing the transistor to block reverse current during dead periods while maintaining proper forward conduction during active operation, thereby preventing body diode current and interference with neighboring devices
Solution Approach 2:
Different portions of the channel region are doped with different doping concentrations to create localized electrical properties. The first portion has a first doping concentration optimized for forward conduction, while the second portion has a second doping concentration that raises the threshold voltage to prevent reverse conduction during dead periods. This local differentiation of electrical properties solves the contradiction between maintaining operation reliability and preventing harmful interference
2Object-generated harmful factors
If the spacing between IC devices is increased to reduce interference, then interference with neighboring devices is reduced, but the IC area increases
Solution Approach 1:
The asymmetric doping structure creates a transistor with different threshold voltages for forward and reverse conduction. This allows the transistor to inherently block reverse current during dead periods, eliminating the need for increased spacing between devices to prevent interference. The solution addresses interference at the device level rather than requiring spatial separation, thus reducing the overall IC area while maintaining low interference levels
3Object-generated harmful factors
If a higher forward threshold voltage is used to prevent reverse current, then interference is reduced, but the time to raise voltage during activation increases
Solution Approach 1:
The channel region is divided into portions with different doping concentrations: the first portion has a doping concentration optimized for fast switching and low activation time, while the second portion has a higher doping concentration that prevents reverse conduction. This local optimization allows the transistor to achieve both fast activation (through the first portion) and reverse current blocking (through the second portion), resolving the contradiction between interference reduction and activation speed
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution reduces interference with neighboring devices, allows closer device spacing, and enhances the efficiency of the buck converter by minimizing power consumption and reducing the time required to raise the voltage during activation.
Implementation Method 1
a doping extension region adjacent the LDD region, wherein the doping extension region extends farther under the gate structure than the LDD region
Data Source
AI summary
A transistor includes a gate structure over a substrate, wherein the substrate includes a channel region. The transistor further includes a source/drain (S/D) in the substrate adjacent to the gate structure. The transistor further includes a lightly doped drain (LDD) region adjacent to the S/D, wherein a dopant concentration in the first LDD is less than a dopant concentration in the S/D. The transistor further includes a doping extension region adjacent the LDD region, wherein the doping extension region extends farther under the gate structure than the LDD region, and a maximum depth of the doping extension region is 10-times to 30-times greater than a maximum depth of the LDD.