Asymmetric Threshold Voltages via Dipole-Forming Layer
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Solution Overview
Problem
Short-channel field effect transistors (FETs) face challenges in achieving asymmetric threshold voltages due to difficulties in creating a steep potential distribution near the source side, which affects carrier mobility.
Innovation Solution
A method involving the formation of dual spacers around a semiconductor fin, where a dipole-forming layer is introduced in a gap between the spacers, and the inner spacer is etched away, allowing a gate stack to be formed over the semiconductor fin, partially over the dipole-forming layer and partially without it, to create asymmetric threshold voltages by modifying the channel near the drain side with an interfacial dipole layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If asymmetric doping profile is used to add more dopant on the source side, then carrier mobility is enhanced through steeper potential distribution, but it becomes difficult to achieve in short-channel devices
Solution Approach 1:
The patent applies local quality by forming a dipole-forming layer selectively at specific locations (in the gap between spacers, partially under the gate stack) rather than uniformly across the entire channel. This creates localized asymmetric threshold voltage regions near the source side, enhancing carrier mobility where needed without requiring asymmetric doping throughout the short channel, thus resolving the manufacturing difficulty while maintaining the mobility enhancement benefit
Solution Approach 2:
The dipole-forming layer acts as an intermediary element that mediates the threshold voltage asymmetry. Instead of directly applying asymmetric doping to the channel (which is difficult in short-channel devices), the dipole-forming layer is introduced as an intermediate structure that generates the desired asymmetric electric field and threshold voltage profile, thereby achieving the mobility enhancement without the manufacturing complexity of asymmetric doping in short channels
2Productivity
If dipole-forming layer is formed in the gap between spacers, then asymmetric threshold voltage is achieved, but device structure becomes more complex
Solution Approach 1:
The patent applies segmentation by dividing the channel region into distinct zones using spacers and selectively forming the dipole-forming layer in specific segments (in the gap between spacers). This segmented approach allows precise control over where the asymmetric threshold voltage is created, enabling asymmetric threshold voltage control while managing device complexity through modular, localized structure formation rather than requiring complex doping profiles throughout the entire device
3Productivity
If inner spacer is etched away to form gap, then dipole-forming layer can be positioned asymmetrically, but manufacturing process steps increase
Solution Approach 1:
The patent applies preliminary action by forming the inner spacer and outer spacers in a predetermined sequence before final gate stack formation. The inner spacer is temporarily formed to define the gap location, then selectively removed to create the asymmetric positioning region for the dipole-forming layer. This preliminary structuring enables precise asymmetric dipole layer positioning while integrating the additional etching step into the overall fabrication flow in a systematic manner
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively shifts threshold voltages through electric dipoles formed at the interface between the interfacial layer and the dipole layer, enabling control over the ratio of high and low threshold voltage regions, thereby enhancing carrier mobility and device performance.
Implementation Method 1
electric dipoles formed at the interface between the interfacial layer and the dipole layer
Implementation Method 2
field effect transistors (FETs) that have asymmetric threshold voltages across the length of their channels
Data Source
AI summary
Semiconductor devices and methods of forming the same include forming an inner spacer on a semiconductor fin. Two outer spacers are formed around the inner spacer, with one outer spacer being separated from the inner spacer by a gap. A dipole-forming layer is formed on the semiconductor fin in the gap. A gate stack is formed on the semiconductor fin, between the outer spacers.