Asymmetric Transistor Doping Profile for Peak Electric Field Reduction
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Solution Overview
Problem
As transistors are scaled down for high-density devices, their performance deviates from ideal models, leading to issues such as increased peak electric field, short channel effects, and inadequate current delivery in memory address decoders, which are difficult to address with existing designs.
Innovation Solution
The development of asymmetric transistors with a doping profile where dopant density is low at the drain and high at the source, using a combination of large angle tilt implant drain (LATID) and lightly doped drain (LDD) processes, along with a halo implant, to reduce peak electric field and enhance transconductance while maintaining threshold voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If transistors are scaled down for high-density devices, then device density increases, but performance deviates from ideal models with increased peak electric field and short channel effects
Solution Approach 1:
The patent applies asymmetric doping profiles where the source and drain regions have different doping concentrations and profiles. The drain has a specific doping profile designed to reduce peak electric field, while the source has a different profile optimized for carrier injection. This local differentiation of doping quality resolves the contradiction by allowing high density scaling while maintaining performance through region-specific optimization.
Solution Approach 2:
The patent modifies the doping parameters (concentration, depth, profile shape) of the source and drain regions to optimize transistor performance at scaled dimensions. By changing these physical parameters, particularly the asymmetric doping profiles, the device maintains ideal characteristics despite size reduction, resolving the performance deviation issue while achieving high density.
2Reliability
If asymmetric doping profile is used with low drain doping and high source doping, then peak electric field is reduced and transconductance is enhanced, but device structure becomes more complex
Solution Approach 1:
The patent deliberately introduces asymmetry in the doping profiles of source and drain regions. The drain has a doping profile optimized to reduce peak electric field and enhance transconductance, while the source has a different profile. This asymmetric design directly resolves the transconductance enhancement goal while the complexity is managed through systematic fabrication processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces impact ionization by 50%, improves transconductance and body effect by 15%, and maintains adequate current delivery without reducing threshold voltage, thus addressing the performance deviations in scaled transistors.
Implementation Method 1
the semiconductor material doped with a first type of charge carriers along the gate oxide according to an asymmetric doping profile
Implementation Method 2
applying a large angle tilt implant drain (LATID) process to semiconductor material on a drain side of a transistor gate
Data Source
AI summary
Asymmetric transistors and related methods and devices are disclosed. A transistor includes a semiconductor material doped with a first type of charge carriers along the gate oxide according to an asymmetric doping profile with a halo region on a source side. The transistor also includes a source including a lightly doped drain (LDD) on the source side, and a drain having a doping profile of charge carriers of a second type graded in a decreasing manner toward the source side. A method includes applying a large angle tilt implant drain (LATID) process to a drain side, a halo implant process to a source side, and applying an LDD process on the source side. A memory device includes an asymmetric transistor. A computing device includes an asymmetric transistor.