Asymmetric Multi-Gated Transistor FinFET Doping
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Solution Overview
Problem
Current methods for forming asymmetric multi-gated FinFETs are complex and costly, requiring additional masking levels and processes, which complicates the fabrication process.
Innovation Solution
An asymmetric multi-gated transistor is formed by asymmetrically doping a semiconductor fin with varying doping concentrations on different sides, allowing for the formation of gate dielectrics and conductors with distinct properties, reducing process complexity and cost by eliminating the need for extra masking levels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If asymmetric multi-gated FinFETs are formed using conventional methods, then the desired asymmetric device characteristics are achieved, but the fabrication process becomes complicated and costly requiring extra masking levels
Solution Approach 1:
The patent applies local quality by creating different doping concentrations on opposite sides of the semiconductor fin. The first side portion has a first doping concentration while the second side portion has a second doping concentration that differs from the first. This local variation in doping quality enables asymmetric device characteristics without requiring complex asymmetric processing steps, thereby resolving the contradiction between achieving asymmetric characteristics and maintaining simple fabrication processes.
2Adaptability or versatility
If asymmetric multi-gated FinFETs are formed using conventional methods, then the desired asymmetric device characteristics are achieved, but additional masking levels and processes are required increasing cost
Solution Approach 1:
The patent uses local quality by implementing selective doping on opposite sides of the fin with different concentrations. This approach achieves asymmetric device characteristics through a single doping process rather than requiring multiple masking levels and sequential processing steps, thereby reducing manufacturing cost while maintaining the desired asymmetric functionality.
3Ease of manufacture
If symmetric multi-gated FinFETs are used, then the fabrication process is simple, but the device characteristics are fixed and cannot be optimized for different power supply conditions
Solution Approach 1:
The patent resolves this contradiction by maintaining a simple symmetric fabrication process structure while introducing local quality variations through different doping concentrations on opposite sides of the fin. This enables the device to be optimized for different power supply conditions (battery-powered low-power mode vs. AC-powered high-performance mode) without complicating the overall manufacturing process.
Solution Approach 2:
The patent applies parameter changes by varying the doping concentration parameter on opposite sides of the semiconductor fin. The first side portion has a first doping concentration and the second side portion has a second doping concentration that differs from the first. This parameter variation enables adjustable device characteristics for different applications while maintaining a simple fabrication process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The approach simplifies the formation process, reduces costs, and enables optimal trade-offs between power consumption and performance by varying the threshold voltage across different transistor sides, suitable for both low-power and high-performance applications.
Implementation Method 1
The semiconductor fin is asymmetrically doped with a semiconductor dopant. A first side portion of the fin has a high doping concentration and a second side portion opposite therefrom has a lower doping concentration.
Implementation Method 2
a gate dielectric formed on the fin. The gate dielectric comprises a first gate dielectric formed on the first side portion of the fin having a high doping concentration and a second gate dielectric formed on the second side portion of the fin having a lower doping concentration.
Data Source
AI summary
In one embodiment, there is an asymmetric multi-gated transistor that has a semiconductor fin with a non-uniform doping profile. A first portion of the fin has a higher doping concentration while a second portion of the fin has a lower doping concentration. In another embodiment, there is an asymmetric multi-gated transistor with gate dielectrics formed on the semiconductor fin that vary in thickness. This asymmetric multi-gated transistor has a thin gate dielectric formed on a first side portion of the semiconductor fin and a thick gate dielectric formed on a second side portion of the fin.