Asymmetric Trench Gate Source Semiconductor Device
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Solution Overview
Problem
Semiconductor devices with gate and source trenches of equal depths struggle to improve short circuit withstand capability and reduce feedback capacitance due to insufficient depletion layer spread, constraining current paths and capacitance.
Innovation Solution
A semiconductor device design with a trench source structure deeper than the trench gate structure, where the ratio of their depths is between 1.5 and 4.0, allowing the depletion layer to spread further, thereby narrowing current paths and reducing feedback capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If gate trench and source trench are formed at equal depths, then manufacturing is simpler, but short circuit withstand capability cannot be improved and feedback capacitance cannot be reduced
Solution Approach 1:
The patent applies asymmetry by forming the source trench deeper than the gate trench, creating an asymmetric trench structure. The source trench depth is set to 1.5-4.0 times the gate trench depth, allowing the depletion layer to spread sufficiently from the deeper source trench to constrict the short-circuit current path while maintaining manufacturing feasibility through controlled depth ratios.
Solution Approach 2:
The patent changes the depth parameter of the source trench relative to the gate trench, establishing a depth ratio between 1.5 and 4.0. This parameter modification enables the depletion layer to extend far enough to achieve adequate current path constriction and reduce feedback capacitance, while the ratio constraint prevents excessive depth that would complicate manufacturing.
2Reliability
If source trench is formed deeper than gate trench, then depletion layer can spread sufficiently to improve short circuit withstand capability, but device structure becomes more complex
Solution Approach 1:
The patent modifies the depth parameter by forming the source trench deeper than the gate trench, with the depth ratio controlled between 1.5 and 4.0. This enables the depletion layer to spread sufficiently from the source trench to the gate trench region, creating effective current path constriction and improving short circuit withstand capability while avoiding excessive structural complexity.
Solution Approach 2:
The asymmetric trench depth configuration allows the source trench to extend deeper into the semiconductor layer, enabling the depletion layer to originate from a deeper position and spread toward the gate trench. This asymmetric design achieves better electrical performance without requiring complete structural redesign.
3Device complexity
If depletion layer is small in width, then device structure is simpler, but feedback capacitance cannot be reduced
Solution Approach 1:
The patent extends the depletion layer formation into the depth dimension by forming the source trench deeper than the gate trench. This vertical extension allows the depletion layer to spread in the depth direction, increasing its effective width and area. The deeper source trench creates a larger depletion region that effectively reduces the feedback capacitance between gate and drain by increasing the separation distance and depletion area.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enhances short circuit withstand capability and decreases feedback capacitance, improving the device's reliability and switching speed.
Implementation Method 1
a depletion layer can be spread from a boundary region between the semiconductor layer and the deep well region
Implementation Method 2
a gate electrode embedded in the gate trench via a gate insulating layer
Data Source
AI summary
A semiconductor device includes a semiconductor layer of a first conductivity type having a first main surface at one side and a second main surface at another side, a trench gate structure including a gate trench formed in the first main surface of the semiconductor layer, and a gate electrode embedded in the gate trench via a gate insulating layer, a trench source structure including a source trench formed deeper than the gate trench and across an interval from the gate trench in the first main surface of the semiconductor layer, a source electrode embedded in the source trench, and a deep well region of a second conductivity type formed in a region of the semiconductor layer along the source trench, a ratio of a depth of the trench source structure with respect to a depth of the trench gate structure being not less than 1.5 and not more than 4.0, a body region of the second conductivity type formed in a region of a surface layer portion of the first main surface of the semiconductor layer between the gate trench and the source trench, a source region of the first conductivity type formed in a surface layer portion of the body region, and a drain electrode connected to the second main surface of the semiconductor layer.