Asymmetric Band-Gap Tunnel Insulator for Low Voltage Memory Operation
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Solution Overview
Problem
Conventional non-volatile memory devices, such as Flash and SONOS memory cells, face limitations in voltage scalability, power efficiency, speed, and feature size reduction due to high programming voltages that damage tunnel insulation layers and reduce memory cell density, leading to issues with charge retention, endurance, and read speed.
Innovation Solution
The implementation of dual gate or back-side gate non-volatile memory cells with band-engineered gate-stacks that allow for low voltage tunneling programming and erasure, using asymmetric tunnel barriers and high K dielectric materials to reduce the equivalent oxide thickness (EOT) and enhance charge retention, while minimizing damage to the gate-stack and crystal lattice.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high programming voltages are used for conventional non-volatile memory devices, then charge can be injected to floating gates, but tunnel insulation layers are damaged and memory cell density is reduced
Solution Approach 1:
The patent changes the voltage parameter from high voltage (conventional) to low voltage (innovative), enabling direct tunneling at lower voltages that do not damage the tunnel insulation layer. This is achieved through optimized tunnel barrier thickness and material composition, allowing charge injection without the harmful high fields that cause insulation degradation.
Solution Approach 2:
The patent uses composite tunnel barrier structures with multiple layers of different materials (e.g., oxide/nitride/oxide combinations) to achieve both low voltage tunneling capability and high charge retention. The composite structure provides optimized electronic properties that enable direct tunneling at low voltages while maintaining insulation integrity and deep charge trapping.
2Productivity
If high programming voltages are applied, then memory cells can be programmed, but power consumption increases and speed decreases
Solution Approach 1:
The patent changes the voltage parameter from high to low, enabling direct tunneling programming at low voltages. This reduces power consumption significantly while increasing programming speed because the tunneling process occurs directly without requiring high field buildup time, eliminating the delay associated with conventional high voltage programming sequences.
3Area of moving object
If feature size is reduced to increase memory density, then device scaling is achieved, but high programming voltages cause more damage to tunnel insulation
Solution Approach 1:
The patent changes the voltage parameter to low voltage operation, which enables feature size scaling without proportionally increasing tunnel insulation stress. The low voltage direct tunneling mechanism maintains acceptable tunnel insulation electric field levels even as device dimensions shrink, allowing continued scaling while preserving insulation durability and charge retention.
4Ease of manufacture
If conventional tunnel insulation is used, then manufacturing is simpler, but voltage scalability is limited and equivalent oxide thickness cannot be reduced
Solution Approach 1:
The patent employs composite tunnel barrier structures with multiple dielectric layers having different electronic properties. These composite materials provide tailored band offsets and effective oxide thicknesses that enable voltage scalability and direct tunneling at low voltages. The manufacturing processes for these composite structures are compatible with existing semiconductor fabrication techniques, maintaining ease of manufacture while achieving superior electrical characteristics.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables higher density memory devices with improved retention, speed, and endurance, allowing for progressive lithographic scaling and reduced power consumption, while maintaining high charge blocking barriers and deep carrier trapping sites.
Implementation Method 1
Methods of operating memory cell having asymmetric band-gap tunnel insulator using direct tunneling
Data Source
AI summary
Methods of operating dual-gate memory cells having asymmetric band-gap tunnel insulators using direct tunneling. The asymmetric band-gap tunnel insulators allow for low voltage direct tunneling programming and efficient erase with holes and/or electrons, while maintaining high charge blocking barriers and deep carrier trapping sites for good charge retention.