Asymmetric Vertical Transistor Fabrication via Dual Spacer Patterning
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Solution Overview
Problem
Conventional vertical field effect transistors (VFETs) are symmetric, making it challenging to fabricate asymmetric VFETs, which are desirable for applications like floating body memory that require individually controllable transistors with different front and back gates, especially as the fin body becomes thinner.
Innovation Solution
The method involves forming two sets of spacers with different thicknesses to pattern the sides of each fin, using a semiconductor substrate and a different semiconductor material like silicon germanium for one side, resulting in an asymmetric VFET with vertical current flow between source and drain regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional symmetric VFET fabrication methods are used, then manufacturing simplicity is maintained, but the ability to achieve asymmetric transistor structures required for floating body memory is lost
Solution Approach 1:
The fin structure is segmented into two distinct sides with different semiconductor materials (first semiconductor material on one side, second semiconductor material on the other side), allowing each side to be independently controlled by separate gates. This segmentation enables asymmetric transistor functionality while using standardized fabrication processes for each side.
Solution Approach 2:
Different semiconductor materials are applied to different sides of the fin structure based on local requirements. The first side uses a first semiconductor material optimized for front gate control, while the second side uses a second semiconductor material optimized for back gate control, achieving local optimization for floating body memory operation.
2Productivity
If the fin body is made thinner to improve device scaling, then device density increases, but the difficulty of fabricating asymmetric structures increases
Solution Approach 1:
Mandrels are formed preliminary to define the fin structure geometry before the fin body is thinned. This preliminary patterning establishes the asymmetric configuration early in the fabrication process, allowing subsequent thinning steps to maintain the asymmetric structure without requiring ultra-precise control during the thinning process itself.
Solution Approach 2:
Mandrels serve as intermediary structures that guide the formation of asymmetric fins. The mandrels are formed with specific geometries that translate into the desired asymmetric fin shapes after removal, enabling precise asymmetric structure fabrication even when the final fin body is very thin.
Data Source
AI summary
A method of fabricating asymmetric vertical field effect transistors (VFETs) includes forming mandrels above a substrate comprising a first semiconductor material. A first set of spacers is formed adjacent to each side of the mandrels, and trenches are formed in portions of the substrate that are not below one of the mandrels or one of the first set of spacers. The method also includes filling the trenches with a second semiconductor material that is different from the first semiconductor material and forming a second set of spacers adjacent to each respective one of the first set of spacers. The second set of spacers is above the second semiconductor material. A plurality of fins is formed such that each one of the plurality of fins includes a portion of the substrate and a portion of the second semiconductor material. Gates are formed between each adjacent pair of fins.