Asymmetric Via Design for Semiconductor Interconnect Alignment
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Solution Overview
Problem
In the dual damascene process for semiconductor device manufacturing, positional displacement between the trench for the upper-layer interconnect and the hole for the via can lead to a small overlapping area, resulting in copper burying imperfections and voids.
Innovation Solution
The via material is elongated in the longitudinal direction of the interconnect, ensuring a larger overlapping area with the interconnect, thus providing a margin for positional displacement during manufacturing, and is formed using the dual damascene process with a via-first approach to simplify etching and reduce manufacturing complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the via hole is formed as a square shape in the dual damascene process, then the manufacturing process is simple, but the overlapping area between via and interconnect becomes small when positional displacement occurs
Solution Approach 1:
The via hole is formed with an asymmetric rectangular shape where the length in the longitudinal direction of the interconnect (first length) is greater than the length in the perpendicular direction (second length). This asymmetric design ensures that even when positional displacement occurs during etching, the via maintains sufficient overlapping area with the interconnect, preventing copper burying imperfections while keeping the manufacturing process relatively simple.
2Manufacturing precision
If the first length of via material is made larger than the second length, then the overlapping area is expanded and positional displacement margin is ensured, but the via material uses more copper
Solution Approach 1:
The via hole is designed with different dimensions in different directions: the first length in the longitudinal direction of the interconnect is made larger to ensure overlapping area and positional tolerance, while the second length in the perpendicular direction is kept smaller to minimize copper consumption. This local differentiation of dimensions optimizes both manufacturing precision and material efficiency.
Data Source
AI summary
A method for manufacturing a semiconductor device includes forming a first interconnect over the semiconductor substrate; forming an interlayer dielectric film over the first interconnect; forming a hole in the interlayer dielectric film such that the hole reaches the first interconnect; forming a trench in the interlayer dielectric film; and embedded a conductive film in the hole and the trench, thereby a via is formed in the hole and a second interconnect in the trench, wherein, in a planar view, the first interconnect extends in a first direction, wherein, in a planar view, the second interconnect extends in a second direction which is perpendicular to the first direction, and wherein a maximum width of the via in the second direction is larger than a maximum width of the via in the first direction.