Asymmetric Voting Thresholds for SERDES Clock Data Recovery
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Solution Overview
Problem
At-rate clock data recovery in serializer/deserializer (SERDES) circuits faces challenges in accurately determining clocking positions due to factors like clock jitter and noisy data, leading to skew mismatches and bit misalignment, especially in long data channels and high data rates.
Innovation Solution
Implementing a controllable early-late offset system with asymmetric voting thresholds to de-skeew voting results and tune the clock data recovery (CDR) to an optimal position, using an offset circuit to store and adjust advance and retard thresholds for generating advance/retard signals based on pulse signal measurements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional symmetric voting thresholds are used in at-rate CDR, then the system operates with standard decision boundaries, but skew mismatches and bit misalignment occur due to slope asymmetry in the pulse signal
Solution Approach 1:
The patent applies asymmetry by implementing different voting thresholds for advance and retard decisions in the CDR system. Instead of using symmetric thresholds, the system uses an asymmetric threshold pair that compensates for the slope asymmetry in the pulse signal, thereby improving clocking position determination accuracy and reducing bit misalignment
Solution Approach 2:
The patent changes the threshold parameters from symmetric to asymmetric values. The offset circuit stores and applies different threshold values for advance and retard decisions, dynamically adjusting the decision boundaries to match the actual pulse signal characteristics, which improves measurement precision without sacrificing reliability
2Reliability
If the CDR attempts to optimize sampling reliability by shifting clocking locations, then data recovery improves, but clock jitter and noisy data frustrate accurate determination of signal transitions
Solution Approach 1:
The patent introduces an offset circuit as an intermediary element that stores and applies threshold offsets. This intermediary component mediates between the noisy pulse signal and the voting circuit, providing stabilized reference levels that facilitate accurate signal transition detection even in the presence of clock jitter and noise
Solution Approach 2:
The system uses feedback through the voting circuit that counts advance and retard votes based on asymmetric threshold comparisons. This feedback mechanism allows the CDR to iteratively optimize the clocking position by accumulating voting results and adjusting accordingly, improving sampling reliability despite noisy conditions
3Measurement precision
If asymmetric voting thresholds are implemented to de-skew voting results, then CDR locking position tuning improves, but the system complexity increases with additional offset circuitry
Solution Approach 1:
The offset circuit serves multiple functions: it stores the asymmetric threshold values, provides the threshold references to the voting circuit, and enables both advance and retard decision-making with appropriate offsets. This multi-functionality achieves improved CDR locking position accuracy without proportionally increasing system complexity
Data Source
AI summary
Embodiments include systems and methods for applying a controllable early/late offset to an at-rate clock data recovery (CDR) system. Some embodiments operate in context of a CDR circuit of a serializer/deserializer (SERDES). For example, slope asymmetry around the first precursor of the channel pulse response for the SERDES can tend to skew at-rate CDR determinations of whether to advance or retard clocking. Accordingly, embodiments use asymmetric voting thresholds for generating each of the advance and retard signals in an attempt to de-skew the voting results and effectively tune the CDR to a position either earlier or later than the first precursor zero crossing (i.e., h(−1)=0) position. This can improve link margin and data recovery, particularly for long data channels and/or at higher data rates.