Asymmetric Wire Bonding for Semiconductor ON Resistance Reduction
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Solution Overview
Problem
In semiconductor devices, the existing methods for connecting semiconductor elements to terminals often result in increased ON resistance due to the resistance at the joint areas between the source electrode and the bonding wires, which can lead to reduced power conversion efficiency and assembly yield.
Innovation Solution
The semiconductor device employs a wire bonding method where the first joint portions between the bonding wires and the source electrode are longer than the second joint portions between the wires and the terminal, with a staggered arrangement to increase the joint area and prevent interference during the bonding process, using a bonding tool to form loop and wedge bonded portions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional wire bonding methods are used with equal length joint portions, then the bonding process is simple, but the ON resistance increases due to insufficient joint area
Solution Approach 1:
The patent applies asymmetry by making the first joint portions (between bonding wires and source electrode) longer than the second joint portions (between wires and terminal). This asymmetric design increases the joint area at the source electrode side where higher current density occurs, thereby reducing ON resistance without requiring complex additional structures
Solution Approach 2:
The patent applies local quality by differentiating the lengths of joint portions based on their functional requirements. The first joint portions have greater length to provide lower resistance paths for current flow from the source electrode, while the second joint portions have sufficient but not excessive length. This localized optimization of joint portion characteristics reduces overall device resistance
2Productivity
If bonding wires are arranged densely, then productivity increases, but interference occurs during the bonding process
Solution Approach 1:
The patent applies segmentation by dividing the bonding process into distinct stages: forming first joint portions at the source electrode, creating loop portions, and forming second joint portions at the terminal. The staggered arrangement where first joint portions extend further in the wire direction creates natural spacing that prevents interference during bonding while enabling dense wire placement
Solution Approach 2:
The patent resolves the interference problem by utilizing the spatial dimension of joint portion length differentiation. By making first joint portions longer than second joint portions, the invention creates a staggered configuration in the wire direction that provides sufficient clearance for the bonding tool to access and bond adjacent wires without interference, thereby enabling dense wire arrangement
3Loss of energy
If joint area is increased to reduce ON resistance, then power conversion efficiency improves, but the device structure becomes more complex
Solution Approach 1:
The patent reduces ON resistance by implementing asymmetric joint portion lengths where first joint portions (at the source electrode) are longer than second joint portions (at the terminal). This asymmetric configuration increases the effective joint area precisely where it is most needed - at the source electrode side with higher current density - thereby reducing power loss without requiring uniformly complex structures throughout the device
Solution Approach 2:
The patent applies local quality by concentrating the increased joint area at the source electrode side where current density is highest and resistance impact is greatest. The first joint portions have greater length to provide lower resistance paths, while the second joint portions maintain sufficient length without excessive complexity. This localized approach to increasing joint area efficiently reduces ON resistance
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively reduces the ON resistance of the semiconductor device, improves power conversion efficiency, and enhances assembly yield by increasing the joint area and reliability while allowing for a more dense arrangement of bonding wires.
Implementation Method 1
a first joint portion bonded to the source electrode, a loop portion extending between the semiconductor chip and the terminal, and a second joint portion bonded to the terminal
Data Source
AI summary
A semiconductor device includes a semiconductor chip having an electrode pad, a terminal having a terminal pad, and a bonding wire. The bonding wire includes a first end portion, a first bonded portion bonded to the electrode pad, a loop portion extending between the semiconductor chip and the terminal, and a second bonded portion bonded to the terminal pad. The second bonded portion is a wedge bonded portion comprising a second end portion of the bonding wire opposite to the first end portion. A length of the first bonded portion in the first direction is greater than a length of the second bonded portion in the first direction.