Asymmetric Wiring in Package Substrate Corners
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Solution Overview
Problem
Thinner and more compact package substrates in the electronic industry are prone to warpage, which causes reliability issues due to uneven thermal expansion coefficients, leading to potential electrical shorts when mounted on boards.
Innovation Solution
A package substrate design with a core layer, an upper layer having a higher thermal expansion coefficient than the lower layer, where the area proportion of wiring structures in the upper layer is less than in the lower layer, specifically within a 10% to 50% difference, to prevent downward warpage and ensure reliable mounting.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If package substrates are made thinner and more compact, then electronic products can be smaller and lighter, but warpage occurs in corner regions during fabrication processes
Solution Approach 1:
The patent applies local quality by creating asymmetric wiring structure area proportions specifically in corner regions. The upper layer wiring structures have a smaller area proportion (10%-50% less) compared to lower layer wiring structures only in the corner regions, while other regions maintain balanced proportions. This localized asymmetry compensates for thermal expansion differences and prevents warpage in the problematic corner areas without affecting the overall substrate compactness.
Solution Approach 2:
The patent changes the area proportion parameter of wiring structures to control thermal expansion. By reducing the area proportion of upper layer wiring structures relative to lower layer wiring structures in corner regions by 10%-50%, the thermal expansion coefficient of the upper layer becomes greater than that of the lower layer, creating a compensatory effect that prevents warpage while maintaining the thin and compact substrate design.
2Adaptability or versatility
If wiring structures are added to provide electrical connections, then functionality is improved, but thermal expansion differences cause warpage in corner regions
Solution Approach 1:
The patent implements local quality by differentiating the wiring structure area proportions between upper and lower layers specifically in corner regions. The upper layer wiring structures occupy a smaller area proportion (reduced by 10%-50%) compared to lower layer wiring structures in these regions, while maintaining adequate electrical connection capability. This localized adjustment addresses the warpage issue without compromising the overall electrical functionality of the substrate.
Solution Approach 2:
The patent modifies the area proportion parameter of wiring structures in corner regions to control thermal expansion behavior. By reducing the upper layer wiring area proportion by 10%-50% relative to the lower layer, the thermal expansion coefficient of the upper layer becomes greater, creating a compensatory mechanism that prevents warpage while preserving electrical connection capabilities through the adjusted wiring configuration.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design effectively prevents warpage in the corner regions of the package substrate, reducing the risk of electrical shorts and enhancing the reliability of semiconductor packages by managing thermal expansion coefficients.
Implementation Method 1
uneven thermal expansion coefficients, which causes reliability issues
Data Source
AI summary
Disclosed are package substrates and semiconductor packages including the same. A package substrate may have a plurality of corner regions; a core layer having a first surface and a second surface; an upper layer, which includes a plurality of first wiring structures and a plurality of first dielectric layers; and a lower layer, which includes a plurality of second wiring structures and a plurality of second dielectric layers. Additionally, an area proportion of top surfaces of the first wiring structures in the upper layer relative to a top surface of the upper layer on each of the corner regions is less than an area proportion of top surfaces of the second wiring structures in the lower layer relative to a top surface of the lower layer on each of the corner regions.