Asymmetrical Last Level Cache for Heterogeneous Core Scheduling
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Solution Overview
Problem
Conventional cache architectures in heterogeneous computing systems fail to optimize cache resources based on the specific performance characteristics of different core types, leading to inefficiencies in performance and power consumption.
Innovation Solution
Implementing an asymmetrical last level cache configuration, where each core type is paired with a cache that is tailored to its specific requirements, such as a larger cache for high-performance cores and a smaller cache for efficiency cores, allowing for optimized scheduling and resource allocation based on core and cache characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a uniform cache architecture is used for all core types, then device complexity is reduced and ease of manufacture is improved, but performance optimization and energy efficiency deteriorate
Solution Approach 1:
The cache architecture is segmented into multiple last level caches, with each cache dedicated to a specific core type (e.g., performance cores, efficiency cores, graphics cores). This segmentation allows each cache to be optimized independently for its target core type, resolving the contradiction between manufacturing simplicity and performance optimization.
Solution Approach 2:
Each last level cache is configured with local quality characteristics tailored to its associated core type, including customized cache sizes, associativity, and replacement policies. For example, performance cores receive larger, faster caches while efficiency cores receive smaller, more power-efficient caches, enabling optimal performance for each core type without compromising overall system manufacturability.
2Productivity
If larger caches are provided for all cores, then performance is improved, but power consumption increases
Solution Approach 1:
The patent applies local quality by configuring each last level cache with size and performance characteristics locally optimized for its associated core type. High-performance cores receive larger, faster caches to maximize processing speed, while efficiency cores receive smaller, more power-efficient caches, thereby achieving performance optimization without unnecessary power consumption across the entire system.
Solution Approach 2:
The cache architecture transitions from symmetry (uniform caches for all cores) to asymmetry (differentiated caches for different core types). Each core type receives a cache configuration that is asymmetrically tailored to its specific performance and power requirements, allowing the system to optimize the trade-off between processing speed and power consumption for each core type independently.
3Use of energy by moving object
If smaller caches are used to reduce power consumption, then energy efficiency is improved, but performance and throughput deteriorate
Solution Approach 1:
The cache system is segmented into multiple independent last level caches, each serving specific core types. This segmentation allows the system to allocate appropriate cache sizes to different core types based on their performance requirements, ensuring that high-throughput cores receive adequate cache resources while low-power cores use smaller caches, thereby maintaining overall system productivity without excessive power consumption.
Solution Approach 2:
The patent changes key cache parameters (size, associativity, replacement policy) to match the specific requirements of each core type. Performance-critical cores are paired with caches that have larger sizes and higher associativity to maximize throughput, while power-sensitive cores use caches with optimized parameters for energy efficiency, thus resolving the contradiction between power consumption and processing throughput.
4Device complexity
If a single shared cache is used, then device complexity is reduced, but performance optimization for heterogeneous cores deteriorates
Solution Approach 1:
The shared cache concept is transformed into segmented, dedicated caches for different core types. Instead of one monolithic shared cache, the system implements multiple last level caches that are logically separated and dedicated to specific core types, reducing complexity in cache management while enabling performance optimization for each heterogeneous core type.
Solution Approach 2:
Each last level cache is configured with local quality characteristics (size, speed, associativity, replacement policy) that are optimized for its associated core type. This local optimization enables the system to achieve high performance for heterogeneous cores without requiring a complex, dynamically reconfigurable shared cache architecture.
Data Source
AI summary
An asymmetrical last level cache is described. In one or more implementations, a system includes a first set of cores with an associated first last level cache and a second set of cores with an associated second last level cache. The first and second last level caches are asymmetrical, meaning they have differing characteristics such as size, speed, replacement policy, or associativity. This configuration allows for dynamic allocation of tasks to the cores based on a combination of the performance characteristics of the cores and the attributes of their associated last level caches.