Asymmetrical Channel Floating Gate Memory Cell
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Solution Overview
Problem
Three-state one-time programmable nonvolatile memory requires additional complex programming and read circuitry, which can reduce space savings and increase product cost.
Innovation Solution
The electronic device includes a non-volatile memory cell with an asymmetrical channel region and a floating gate structure, allowing for three distinct program states with simple and compact write and read circuitry.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If three-state one-time programmable nonvolatile memory is used to store more data in the same silicon area, then data storage capacity increases, but additional complex programming and read circuitry is required which reduces space savings and increases product cost
Solution Approach 1:
The patent applies asymmetry by creating an asymmetrical channel structure where one channel region has a different doping concentration than the other channel region. This asymmetry enables the memory cell to distinguish between three different programmed states (0, 1, and X states) through differential conductance measurements, eliminating the need for complex additional circuitry while achieving three-state storage capability
Solution Approach 2:
The patent implements local quality by applying different doping concentrations to specific regions of the channel. The first channel region has a first doping concentration while the second channel region has a second doping concentration that is different from the first. This localized variation in material properties enables the asymmetrical conductance characteristics needed for three-state memory operation using simple existing circuitry
2Volume of moving object
If three-state one-time programmable nonvolatile memory is used to increase circuit density, then device size decreases, but additional complex programming and read circuitry is required which increases product cost
Solution Approach 1:
The asymmetrical channel structure with different doping concentrations enables three-state storage in a compact cell design, achieving high circuit density without requiring additional complex programming or read circuitry. The asymmetry is inherent in the transistor structure itself, eliminating the need for extra components
Solution Approach 2:
The patent makes the existing memory cell structure multi-functional by enabling it to store three states (0, 1, and X) through the asymmetrical channel design. The same basic transistor structure and circuitry that would normally support only binary storage now supports ternary storage, achieving density improvement without adding specialized circuitry for each function
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables the storage of more data in the same silicon area, enhances data security, and reduces device size and cost while maintaining increased circuit density.
Implementation Method 1
a gate structure over the channel region and including a gate dielectric layer over the channel region and a floating gate over the gate dielectric layer
Implementation Method 2
implanting dopants of the second conductivity type under the first sidewall of the floating gate while blocking the dopants from the second sidewall of the floating gate; and implanting dopants of an opposite first conductivity type into the substrate adjacent the first and second sidewalls of the gate structure
Data Source
AI summary
An electronic device with a non-volatile memory includes a non-volatile memory (NVM) cell selectively programmable to change a program state from a first state to a second state or to a third state, and may also include a write circuit configured to selectively program the NVM cell to change the program state from the first state to the second state by applying a programming voltage signal to a first source/drain region and to change the program state from the first state to the third state by applying the programming voltage signal to a second source/drain region. A read circuit is configured to identify the program state of the NVM memory cell as one of the first state, the second state, and the third state based on a cell voltage of the non-volatile memory cell.