Asymmetrical Clock Duty Cycle for Lower Flip-Flop Dynamic Power
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Solution Overview
Problem
Integrated circuits face challenges in minimizing dynamic power consumption, which affects battery life due to significant power usage during normal operation, particularly in transistors.
Innovation Solution
Incorporating an asymmetrical clock generation circuitry that provides an asymmetrical clock with a duty cycle greater than 50% to inhibit intermediate data transitions through master portions of storage elements, utilizing a counter-based divider circuit and phase delay circuit for fine adjustments, effectively reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If asymmetrical clock generation circuitry is used to reduce dynamic power consumption, then power savings are achieved, but device complexity increases
Solution Approach 1:
The patent applies asymmetry by generating clock signals with unequal high and low periods (duty cycle > 50%). The asymmetrical clock generation circuitry produces a first clock signal where the high period exceeds the low period, creating an asymmetric timing pattern that selectively enables master portions of storage elements during the extended high period, thereby reducing dynamic power consumption by preventing unnecessary intermediate data transitions.
Solution Approach 2:
The patent segments the clock generation function into distinct components: an asymmetrical clock generation circuitry that produces the unequal duty cycle clock signal, and a duty cycle control circuit that further refines the timing. This segmentation allows independent optimization of each component's power characteristics while achieving overall power reduction.
2Loss of energy
If duty cycle control circuitry is added for fine adjustments, then power consumption is reduced, but device complexity increases
Solution Approach 1:
The duty cycle control circuitry introduces dynamic adjustability to the clock signal timing. By enabling fine adjustments to the duty cycle, the system can adaptively optimize power consumption based on operational conditions while maintaining proper synchronization. This dynamic control allows the circuit to achieve minimal power consumption by precisely timing when master portions are enabled.
Solution Approach 2:
The patent changes the temporal parameters of the clock signal by implementing variable duty cycle control. The duty cycle control circuitry modifies the high period and low period durations of the clock signal, creating parameter variations that optimize the timing for power reduction while maintaining functional correctness of the storage elements.
Data Source
AI summary
An integrated circuit includes a master-slave storage element having a data input coupled to receive a data signal and an asymmetrical clock generator coupled to provide an asymmetrical clock signal to the master-slave storage element. A first phase of the asymmetrical clock signal is configured for inhibiting intermediate data signal transitions from propagating through the master portion of the master-slave storage element.