Asymmetrical Clocking for Lower Flip-Flop Dynamic Power
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Solution Overview
Problem
Integrated circuits consume significant dynamic power due to intermediate data transitions through master portions of storage elements, necessitating improved low power techniques to extend battery life.
Innovation Solution
Implementing asymmetrical clock generation circuitry to generate a clock signal with a duty cycle greater than 50%, inhibiting intermediate data transitions in master portions of storage elements like D-type flip flops, using a counter-based divider and phase delay circuit to adjust the duty cycle.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If asymmetrical clock generation circuitry is implemented to generate a clock signal with a duty cycle greater than 50%, then dynamic power consumption is reduced by inhibiting intermediate data transitions, but device complexity increases due to the additional counter-based divider and phase delay circuit
Solution Approach 1:
The patent applies asymmetry by generating a clock signal with an asymmetrical duty cycle (greater than 50%) instead of a conventional 50% duty cycle. This asymmetrical clocking scheme inhibits intermediate data transitions in master portions of storage elements, thereby reducing dynamic power consumption. The asymmetrical clock generation circuitry includes a counter-based divider and phase delay circuit that work together to produce the asymmetrical clock signal with the desired duty cycle.
2Adaptability or versatility
If a counter-based divider circuit is used to generate the asymmetrical clock signal, then the duty cycle can be precisely controlled to track process, voltage, and temperature variations, but manufacturing precision requirements increase
Solution Approach 1:
The patent applies dynamics by designing a clock generation system that dynamically adapts to process, voltage, and temperature variations. The counter-based divider circuit is configured to adjust the duty cycle of the asymmetrical clock signal in response to changing operating conditions, ensuring optimal power savings across different environmental conditions. This dynamic adaptation allows the system to maintain effective inhibition of intermediate data transitions despite variations in manufacturing parameters.
3Loss of energy
If the asymmetrical clock signal is applied to master-slave storage elements, then intermediate data transitions are inhibited and power savings are achieved, but the clock signal generation requires additional circuitry
Solution Approach 1:
The patent applies merging by integrating the counter-based divider and phase delay circuit into a unified asymmetrical clock generation system. These circuits work together to produce the asymmetrical clock signal that is distributed to multiple master-slave storage elements. By combining these functions into a coordinated system, the patent achieves effective power savings through inhibition of intermediate data transitions while managing the added circuitry through systematic integration.
Data Source
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AI summary
An integrated circuit includes a master-slave storage element having a data input coupled to receive a data signal and an asymmetrical clock generator coupled to provide an asymmetrical clock signal to the master-slave storage element. A first phase of the asymmetrical clock signal is configured for inhibiting intermediate data signal transitions from propagating through the master portion of the master-slave storage element.