Asymmetrical CMOS Transistor Source Drain Regions for Dark Current Reduction
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Solution Overview
Problem
Conventional CMOS image sensors suffer from reduced charge transmission efficiency and charge storage capacity due to noise and dark currents, primarily caused by hot carriers from transistors, which degrade image quality.
Innovation Solution
The design includes a semiconductor substrate with a photo-detector and specific transistor configurations, such as reset and source-follower transistors with asymmetrical lightly doped source and drain regions, to reduce dark current generation. These transistors are fabricated using a process that involves ion-implantation masks and spacers to form asymmetrical lightly doped regions, improving charge handling and transfer efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional CMOS transistors with symmetrical source and drain regions are used, then manufacturing is simple, but dark current generation increases due to hot carriers
Solution Approach 1:
The patent applies asymmetry by forming lightly doped source and drain regions with different widths in CMOS transistors. Specifically, one lightly doped region has a greater width than the other, creating an asymmetric structure that reduces hot carrier generation and subsequently reduces dark current in the photodetector, while still using conventional fabrication processes
2Object-generated harmful factors
If asymmetrical lightly doped source and drain regions are formed, then dark current is reduced, but device structure becomes more complex
Solution Approach 1:
The patent applies local quality by modifying only specific regions of the transistor structure - the lightly doped source and drain regions - while keeping the rest of the transistor structure conventional. This localized modification creates the asymmetric structure needed to reduce dark current without fundamentally changing the entire device architecture
3Ease of manufacture
If conventional ion implantation without asymmetrical masking is used, then manufacturing process is simple, but charge transmission efficiency decreases
Solution Approach 1:
The patent applies segmentation by dividing the ion implantation process into separate steps for forming source and drain regions. Different masking patterns are used for each region, allowing independent control of doping profiles and creating the asymmetric structure that improves charge transmission efficiency while using standard fabrication techniques
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces dark current generation, enhancing the image quality by improving charge transfer and storage capabilities in CMOS image sensors.
Implementation Method 1
a photo-detector includes a charge-generating region therein that is configured to convert photons received by the photo-detector into charge carriers
Implementation Method 2
These transistors are fabricated using a process that involves ion-implantation masks and spacers to form asymmetrical lightly doped regions
Data Source
AI summary
Image sensor devices are provided having reduced dark current generation characteristics. These image sensor devices include a semiconductor substrate and a photo-detector therein (e.g., P-N photodiode). The photo-detector includes a charge-generating region therein that is configured to convert photons received by the photo-detector into charge carriers. A first transistor, which has a terminal configured to receive the charge carriers generated by the photo-detector, is also provided. The first transistor includes a first gate electrode and a first pair of lightly doped source and drain regions of unequal width on opposite sides of the first gate electrode. This first transistor may be a three-terminal device and the terminal that is configured to receive the charge carriers may be selected from a group consisting of a gate, source and drain terminals. In particular, the first transistor may be configured as a reset transistor or as a source-follower transistor.