Asymmetrical Contact Arrays for Semiconductor Device Fabrication
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Solution Overview
Problem
As semiconductor devices integrate more densely, the reduced pitch in patterns and transistor size lead to a short channel effect, necessitating innovative contact structures to enhance channel length and reduce contact resistance, which existing technologies struggle to address effectively.
Innovation Solution
A method of fabricating semiconductor devices using asymmetrical contact arrays with a zigzag structure formed by double patterning technology (DPT), where conductive line layers are etched to create trenches and filled with a gap filling layer, forming spacers and conductive landing pads aligned in a zigzag pattern to increase contact area and reduce resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional contact structures are used in densely integrated semiconductor devices, then manufacturing process remains simple, but contact resistance increases and channel length is insufficient
Solution Approach 1:
The contact structure is segmented into multiple components including asymmetrical contact arrays with zigzag patterns, multiple conductive line layers, and spacer structures. This segmentation increases the effective contact area with active regions, thereby reducing contact resistance and improving electrical reliability without requiring overly complex manufacturing processes
Solution Approach 2:
The patent employs asymmetrical contact arrays where contact holes are positioned at different locations relative to active regions, creating unequal spacing patterns. This asymmetry optimizes the contact area with respect to the active region geometry, effectively reducing contact resistance while maintaining compatibility with standard fabrication processes
2Productivity
If transistor size is reduced to increase integration density, then device integration increases, but short channel effect worsens
Solution Approach 1:
The patent extends the contact structure into multiple vertical layers with conductive line layers at different heights, creating a three-dimensional contact architecture. This dimensional extension increases the effective contact area and length without increasing the planar footprint, thereby maintaining high integration density while improving channel length and reducing short channel effects
3Area of stationary object
If symmetrical contact arrays are used, then manufacturing process is simple, but contact area with active regions is insufficient
Solution Approach 1:
The patent deliberately introduces asymmetry in the contact array design where contact holes are positioned at different locations and with different spacing relative to active regions. This asymmetrical configuration maximizes the contact area with the active region boundaries, and the fabrication process uses corresponding asymmetrical mask patterns that can be implemented using standard photolithography techniques
4Productivity
If pitch in patterns is reduced to increase integration, then device density increases, but manufacturing precision requirements increase
Solution Approach 1:
The contact structure is divided into multiple discrete elements including individual contact holes, spacer structures, and conductive line segments. This segmentation allows each element to be formed with standard pitch requirements while the collective arrangement achieves high device density, effectively distributing the precision requirements across multiple manufacturable features rather than requiring ultra-fine single-feature precision
Data Source
AI summary
A method uses a line pattern to form a semiconductor device including asymmetrical contact arrays. The method includes forming a plurality of parallel first conductive line layers extending in a first direction on a semiconductor substrate. In this method, the semiconductor substrate may have active regions forming an oblique angle with the first direction. The method may further include forming a first mask layer and a second mask layer and using the first mask layer and the second mask layer to form a trench comprising a line area and a contact area by etching the first conductive line layers using the first mask layer and the second mask layer. The method further includes forming a gap filling layer filling the line area of the trench and forming a spacer of sidewalls of the contact area and forming a second conductive line layer electrically connected to the active region.