Asymmetrical Control Gate Structure for Leakage Current Reduction
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Solution Overview
Problem
Conventional methods for manufacturing EEPROM cells face challenges in extending the length of the control gate to reduce leakage current, as it is difficult to change the thickness of the poly layer used to form the control gate, limiting the ability to effectively prevent leakage current, especially at high temperatures.
Innovation Solution
The non-volatile memory device employs an asymmetrical control gate structure with a first control gate and a second control gate connected to each other, where the second control gate has a wider width, extending further than the first control gate insulating layer, allowing for controlled extension of the control gate length through the etching-back process, and includes a manufacturing method that forms a conductive layer and control gate pattern to achieve this asymmetrical structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-generated harmful factors
If the thickness of the poly layer is changed to extend the control gate length, then the leakage current is reduced, but the manufacturing complexity increases
Solution Approach 1:
The control gate is divided into two separate gates (first control gate and second control gate) with different widths. The second control gate has a greater width than the first control gate, allowing each gate to be optimized independently for reducing leakage current while maintaining standard poly layer thickness and manufacturing processes.
2Reliability
If the control gate length is extended to reduce leakage current, then the reliability improves, but the manufacturing precision requirements increase
Solution Approach 1:
The control gate structure transitions from uniform to non-uniform, with the second control gate having a greater width than the first control gate. This local variation in gate width allows optimized leakage current prevention in critical regions while maintaining standard dimensions in other areas, reducing overall manufacturing precision requirements.
3Object-generated harmful factors
If the poly layer thickness is modified to form a longer control gate, then the leakage current decreases, but the ease of manufacture deteriorates
Solution Approach 1:
The control gate is designed with asymmetric dimensions where the second control gate has a greater width than the first control gate. This asymmetry is achieved through standard photolithography and etching processes without requiring changes to poly layer thickness, maintaining ease of manufacture while effectively reducing leakage current.
Data Source
AI summary
A non-volatile memory device and a method of manufacturing the non-volatile memory device, where the non-volatile memory device includes a floating gate insulating layer and a floating gate disposed on a substrate, a dielectric layer formed perpendicular to the floating gate insulating layer and at two sides of the floating gate, and a first control gate at a first side of the dielectric layer distal from the floating gate and a second control gate at a second side of the dielectric layer distal from the floating gate, wherein the first control gate and the second control gate are connected to each other, and a second width of the second control gate is wider than a first width of the first control gate. A length of a control gate of a non-volatile memory device may be extended to effectively preventing the generation of leakage current when a control gate is off.