Asymmetrical Dislocation in Semiconductor Source-Drain Regions
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Solution Overview
Problem
Current planar FETs fail to meet the requirements of miniaturized consumer electronic products due to limitations in size reduction, leading to the development of non-planar Fin-FETs with three-dimensional channel structures, which aim to improve performance but still face challenges in scaling down further.
Innovation Solution
A semiconductor structure with an asymmetrical dislocation in the source/drain region, integrated into both non-planar and planar transistors, featuring a substrate with a gate structure and source/drain regions, where the dislocation is positioned asymmetrically relative to the middle axis, enhancing control over the channel region and reducing drain-induced barrier lowering and short channel effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If planar FETs are continuously miniaturized, then device size is reduced, but electrical performance deteriorates due to short channel effects and drain-induced barrier lowering
Solution Approach 1:
The patent transitions from planar (2D) FET architecture to three-dimensional Fin-FET architecture by introducing vertical fins that extend from the substrate surface. This dimensional change increases the effective channel width and gate control area without increasing the planar footprint, thereby maintaining electrical performance while enabling further miniaturization of the device footprint.
Solution Approach 2:
The patent introduces asymmetrical dislocation in the source/drain region, positioned closer to one gate than the other. This asymmetrical configuration allows for optimized control of the channel region, reducing drain-induced barrier lowering and short channel effects while maintaining compact device dimensions.
2Reliability
If non-planar Fin-FET structures are adopted, then gate control over channel region is improved, but device complexity increases
Solution Approach 1:
The patent divides the source/drain region into distinct segments with different dislocation characteristics. The asymmetrical dislocation is positioned specifically in one portion of the source/drain region, allowing independent optimization of different areas. This segmentation enables improved gate control in critical regions while maintaining simpler structures in other areas, thereby reducing overall manufacturing complexity.
Solution Approach 2:
The patent applies asymmetrical dislocation locally in specific portions of the source/drain region rather than uniformly throughout. This localized modification provides enhanced gate control and reduced short channel effects only where needed, while maintaining standard structures in other regions, thus balancing performance improvement with manufacturing simplicity.
Data Source
AI summary
The present invention provides a semiconductor structure, comprising a substrate, a gate structure, a source/drain region and at least a dislocation. The gate structure is disposed on the substrate. The source/drain region is disposed in the substrate at two sides of the gate structure. The dislocation is located in the source/drain region, and is asymmetrical relating to a middle axis of the source/drain region.