Asymmetrical Doped Non-Volatile Memory Cell Structure
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Solution Overview
Problem
Conventional PHINES type flash memory cells face issues with slow programming speed, high read-out bias voltage requirements, and increased area occupation due to bit line selection transistors, leading to reduced packing density and reliability.
Innovation Solution
A non-volatile memory cell with an asymmetrical doped structure, featuring a lightly doped region and a pocket-doped region, which allows for increased programming speed and reduced read-out bias voltage, while eliminating the need for multiple bit line selection transistors by using a single group of bit lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If PHINES type flash memory cell uses uniform doped structure, then manufacturing is simplified, but programming speed is slow
Solution Approach 1:
The patent applies asymmetry by introducing different doping structures on opposite sides of the charge-trapping layer. Specifically, a first doped structure (lightly doped region) is formed on one side and a second doped structure (pocket-doped region) is formed on the other side, creating an asymmetrical doped configuration that enhances carrier injection efficiency and programming speed while maintaining manageable device complexity
Solution Approach 2:
The patent implements local quality by varying the doping concentration and type in different regions. The lightly doped region has lower doping concentration while the pocket-doped region has higher doping concentration, allowing each region to be optimized for its specific function in the programming process, thereby improving overall programming speed without requiring complete redesign of the entire device structure
2Quantity of substance
If PHINES type flash memory cell stores data near both drain and source regions, then data storage capacity is increased, but second bit effect occurs causing threshold voltage drop
Solution Approach 1:
The patent uses asymmetry to differentiate the roles of source and drain regions through unequal doping structures. The first doped structure (lightly doped) and second doped structure (pocket-doped) create an asymmetrical configuration that enables selective carrier injection from one region while suppressing injection from the other, thereby preventing the second bit effect and maintaining threshold voltage stability during reverse reading operations
Solution Approach 2:
The patent applies local quality by assigning different doping characteristics to specific regions. The lightly doped region on one side and the pocket-doped region on the other side create localized electrical properties that control carrier injection behavior, allowing data to be stored near both regions while preventing unwanted threshold voltage drops through region-specific doping optimization
3Measurement precision
If PHINES type flash memory cell uses high read-out bias voltage, then reading capability is maintained, but read-out interference is intensified
Solution Approach 1:
The patent implements local quality through asymmetrical doping structures that create different electrical characteristics in source and drain regions. This local differentiation enables one region to serve as a preferred injection path while the other acts as a barrier, allowing reading operations to be performed at lower bias voltages without significant loss of reading capability, thereby reducing read-out interference on neighboring cells
4Adaptability or versatility
If three sets of bit line selection transistors are used for programming, then programming functionality is complete, but area occupation is large reducing packing density
Solution Approach 1:
The patent extracts and eliminates the need for multiple bit line selection transistors by utilizing the asymmetrical doped structure itself to provide the selection function. The different doping regions naturally create directional carrier injection paths, allowing a single group of bit line selection transistors to control the programming operation, thereby removing the redundant transistor sets and significantly reducing the overhead area
Solution Approach 2:
The asymmetrical doped structure serves multiple functions simultaneously: it enables directional carrier injection for programming, provides data storage capability near both source and drain regions, and acts as a natural selection mechanism that replaces the need for additional selection transistors. This multi-functionality reduces the overall device complexity and area occupation while maintaining complete programming functionality
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enhances programming speed, prevents neighboring cell disturb issues, and simplifies the memory cell structure, reducing area occupation and improving read-out efficiency without affecting reading capacity.
Implementation Method 1
a first conductive state of source and drain, a first conductive state of lightly doped region and a second conductive state of pocket-doped region
Implementation Method 2
a charge-trapping layer over the substrate
Data Source
AI summary
A non-volatile memory cell comprising a substrate, a charge-trapping layer, a control gate, a first conductive state of source and drain, a lightly doped region and a second conductive state of pocket-doped region. The charge-trapping layer and the control gate are disposed over the substrate. A dielectric layer is disposed between the substrate, the charge-trapping layer and the control gate. The source and drain are disposed in the substrate on each side of the charge-trapping layer. The lightly doped region is disposed on the substrate surface between the source and the charge-trapping layer. The pocket-doped region is disposed within the substrate between the drain and the charge-trapping layer. Because there are asymmetrical configuration and different doped conductive states of implant structures, the programming speed of the memory cell is increased, the neighboring cell disturb issue is prevented, and the area occupation of the bit line selection transistor is reduced.