Asymmetrical Floating Gate Layout for Higher NVM Coupling Ratio
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Solution Overview
Problem
The miniaturization of semiconductor devices leads to a decrease in device performance due to a lower coupling ratio between the floating gate and the control gate, affecting program and erase efficiency in non-volatile memory (NVM) devices.
Innovation Solution
The implementation of non-volatile memory devices with asymmetrical floating gates, featuring a device portion over the channel region and a coupling portion with multiple sections over the drain region, enhancing capacitive coupling and increasing the overall coupling ratio.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the non-volatile memory device is miniaturized to meet demand for smaller devices, then the device size is reduced, but the coupling ratio between floating gate and control gate decreases
Solution Approach 1:
The floating gate is designed with an asymmetrical structure where the width varies along the channel region. Specifically, the floating gate has a first width at a first location and a second width at a second location, with the second width being greater than the first width. This asymmetry allows the floating gate to maintain a larger effective area for capacitive coupling with the control gate in the miniaturized device, thereby preserving the coupling ratio despite overall device size reduction.
Solution Approach 2:
The floating gate structure implements local quality by having different widths at different locations along the channel. The region over the drain has a greater width than the region over the source, creating localized variations in capacitive coupling strength. This allows optimal coupling ratio in critical regions while maintaining overall device miniaturization.
2Volume of moving object
If the device dimensions are reduced for miniaturization, then smaller device size is achieved, but program and erase efficiency decreases
Solution Approach 1:
The asymmetrical floating gate structure with varying width along the channel enhances the electric field distribution during program and erase operations. The greater width over the drain region creates stronger capacitive coupling in that area, improving charge injection efficiency during programming while maintaining efficient charge removal during erasing, thus preserving productivity in miniaturized devices.
Solution Approach 2:
The floating gate width parameter is changed along its length, transitioning from a uniform width in conventional designs to a variable width where the second width (over drain) exceeds the first width (over source). This parameter variation optimizes the electric field strength and charge distribution, maintaining program and erase efficiency despite reduced device dimensions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design improves the capacitive coupling ratio, allowing for stronger vertical electric fields during programming and erasing, enabling higher program efficiency and potentially lower operating voltages while maintaining device speed.
Implementation Method 1
enhancing capacitive coupling and increasing the overall coupling ratio
Implementation Method 2
allowing for stronger vertical electric fields during programming and erasing
Data Source
AI summary
A non-volatile memory device is provided. The non-volatile memory device includes a substrate having an active region, a source region, a drain region, and a floating gate. The source region and the drain region may be arranged in the active region, the drain region may be arranged adjacent to the source region. The source region and the drain region may define a channel region therebetween. The floating gate may be arranged over the active region, and may include a first section over the channel region, a plurality of second sections over the drain region, and a connecting section arranged between the first section and the plurality of second sections.