Asymmetrical Gate Cut Spacing for Wider Transistor Channels
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Solution Overview
Problem
As integrated circuits shrink in size, forming gate cuts between densely packed transistors becomes challenging due to limitations in current fabrication technology, leading to issues with gate structure isolation and control over channel regions.
Innovation Solution
The technique involves placing gate cuts asymmetrically relative to adjacent channel regions, allowing for varying distances between the gate cuts and channel regions, which increases the acceptable margin of error in mask placement, enabling wider channel regions and improved device performance by allowing the gate electrode to wrap around nanoribbons or nanowires more effectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If gate cuts are placed symmetrically between adjacent transistor devices, then manufacturing precision is improved, but device density and performance are limited due to insufficient channel width
Solution Approach 1:
The patent applies asymmetry by positioning gate cuts at different distances from adjacent channel regions. Specifically, a first gate cut is positioned at a first distance from a first channel region, while a second gate cut is positioned at a second distance from a second channel region, where the first and second distances are different. This asymmetric placement allows one channel region to be wider than the other, thereby increasing the effective channel width for improved device performance while maintaining acceptable manufacturing precision through deliberate design rather than symmetric constraints
2Productivity
If transistors are packed more densely to reduce inter-device spacing, then device density is improved, but gate structure isolation and control become challenging
Solution Approach 1:
The patent applies local quality by allowing different gate cut positions for different transistor devices. Instead of applying a uniform symmetric gate cut placement across all devices, the invention permits asymmetric positioning where specific gate cuts can be placed at optimized distances from their respective channel regions. This local optimization enables better gate control and isolation for each individual device while maintaining high overall device density
3Productivity
If channel regions are made wider to increase drive current, then device performance is improved, but inter-device spacing and gate cut formation become more challenging
Solution Approach 1:
The patent resolves this contradiction by enabling asymmetric gate cut placement that accommodates wider channel regions. By positioning gate cuts at non-uniform distances from adjacent channels, the design allows certain channel regions to be made wider for improved drive current and device performance, while the asymmetric gate cut positions maintain sufficient spacing and isolation for manufacturability
Data Source
Figure 1A
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Figure 1C
AI summary
An integrated circuit includes a first device (101c) and a laterally adjacent second device (101d). The first device includes a first body (104c) including semiconductor material extending from a first source region to a first drain region, and a first gate structure (125b) on the first body. The second device includes a second body (104d) including semiconductor material extending from a second source region to a second drain region, and a second gate structure (125c) on the second body. A gate cut (122b') including dielectric material (124) is between and laterally separates the first gate structure and the second gate structure. The first body is separated laterally from the gate cut by a first distance (d3'), and the second body is separated laterally from the gate cut by a second distance (d4'). The first and second distances differ by at least 2 nanometers. In an example, the first and second devices are fin-based devices or gate-all-around devices.