Asymmetrical Interconnect PHY Testing via Traffic Generator

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Solution Overview

Problem

Existing testing methods for high-speed interconnects, such as UniPro and LLI, are inadequate for asymmetrical interfaces, as loopback testing does not provide sufficient coverage due to differing capabilities between UpLink and DownLink, and requires individual configuration of the DownLink PHY, which is complex and not supported by standard logical analyzers.

Innovation Solution

The use of a traffic generator/analyzer (TGA) to establish a PHY testing mode during link startup, allowing for configuration and transmission of test sequences on identified lanes, enabling effective testing of asymmetrical interconnects by adapting the interface to use TGA for PHY testing instead of loopback.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of operation

If loopback testing is used for asymmetrical interfaces, then testing simplicity is maintained, but testing coverage is insufficient

Engineering Contradiction:
Improvetesting simplicityVSAvoidtesting coverage
Core Design Contradiction:
Ease of operationVSReliability

Solution Approach 1:

The patent introduces a traffic generator/analyzer (TGA) as an intermediary testing device that mediates between the tester and the asymmetrical interface. The TGA generates test patterns and analyzes responses, enabling comprehensive PHY testing of asymmetrical interfaces where traditional loopback fails. This intermediary provides both the electrical/timing accuracy needed for PHY testing and the protocol interaction capability needed for asymmetrical configurations.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Measurement precision

If individual DownLink PHY configuration is implemented for asymmetrical interfaces, then testing accuracy is improved, but device complexity increases

Engineering Contradiction:
Improvetesting accuracyVSAvoidconfiguration complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent implements self-service through automatic configuration mechanisms where the TGA automatically configures the DownLink PHY parameters based on the asymmetrical interface requirements. The system performs self-diagnosis and self-adjustment of testing parameters, eliminating the need for manual configuration of lane counts, data rates, and encoding schemes. This reduces configuration complexity while maintaining testing accuracy through automated parameter optimization.

Inventive Principle:
Principle #25Self-service

3Ease of operation

If standard logical analyzers are used for protocol testing, then ease of operation is maintained, but capability to handle complex protocol interactions is lost

Engineering Contradiction:
Improveease of useVSAvoidprotocol interaction capability
Core Design Contradiction:
Ease of operationVSAdaptability or versatility

Solution Approach 1:

The patent merges the capabilities of logical analyzers with enhanced protocol implementation into a unified TGA system. This combined device retains the ease of use and signal analysis capabilities of standard logical analyzers while adding sophisticated protocol interaction abilities. The TGA can generate ill patterns, drive the Device under Test into corner cases, and handle complex protocol sequences, effectively combining the strengths of both traditional logical analyzers and advanced protocol testers.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS9141496B2Methods and systems for testing electrical behavior of an interconnect having asymmetrical link
Publication Date: 2015.09.22 TELEFONAKTIEBOLAGET LM ERICSSON (PUBL)
  • US9141496B2 patent drawing
  • US9141496B2 patent drawing
  • US9141496B2 patent drawing

AI summary

Methods and devices for testing a physical layer (PHY) of an asymmetrical interconnect interface using a traffic generator/analyzer (TGA) are described. At least one special PHY test sequence is transmitted to the asymmetrical interconnect interface during link start up to place the device under test in PHY testing mode in which the TGA is used to generate and analyze data. The asymmetrical interconnect interface can then receive a configuration command and configure the asymmetrical interconnect interface in response to the configuration command. The asymmetrical interconnect interface can then use the TGA to transmit test sequences to, or receive test sequences from, e.g., a tester, on at least one identified lane of the asymmetrical interconnect device, which at least one identified lane is set by the configuration command.