Asymmetrical I/O Structure for Voltage Withstanding and Speed
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Solution Overview
Problem
Current integrated circuit (IC) input/output (I/O) structures are symmetrical, leading to performance degradation and reliability issues as manufacturing processes advance, particularly in high-speed applications where operating voltages are lower than power supply voltages, and differences in NMOS and PMOS transistor characteristics affect service cycles.
Innovation Solution
An asymmetrical I/O structure is introduced, comprising a first power supply node connected to a higher voltage and a second power supply node connected to a lower voltage, with a pull-up unit and a pull-down unit connected between them, where the number of pull-up transistors differs from the number of pull-down transistors, allowing for optimized signal interaction through specific transistor configurations and voltage connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If stacked design is adopted to meet voltage withstanding requirements, then reliability is improved, but performance degradation occurs
Solution Approach 1:
The patent applies asymmetry by using different numbers of transistors in the pull-up and pull-down paths. Specifically, when the operating voltage is lower than the power supply voltage, the pull-up path uses fewer transistors than the pull-down path, creating an asymmetrical structure that optimizes both reliability and performance for high-speed interfaces
2Manufacturing precision
If separate manufacturing processes are used for NMOS and PMOS transistors, then manufacturing precision is improved, but reliability differences increase
Solution Approach 1:
The patent applies local quality by recognizing that NMOS and PMOS transistors have different manufacturing processes and reliability characteristics, and accordingly designs different path structures for pull-up and pull-down. The asymmetrical design allows each path to be optimized according to its specific transistor type and manufacturing characteristics
3Device complexity
If symmetrical structure is used, then device complexity is reduced, but performance degradation occurs in advanced nodes
Solution Approach 1:
The patent transitions from symmetrical to asymmetrical structure in advanced technology nodes. When the operating voltage is lower than the power supply voltage, the pull-up and pull-down paths use different numbers of transistors, creating an asymmetrical configuration that improves performance for high-speed interfaces while accepting increased complexity
Data Source
AI summary
An asymmetrical I/O structure is provided. In one embodiment, the asymmetrical I/O structure comprises a first power supply node connected to a first voltage, a second power supply node connected to a second voltage, a pull-up unit and a pull-down unit which are connected between the first power supply node and the second power supply node. The first voltage is higher than the second voltage. A node between the pull-up unit and the pull-down unit is connected to an I/O node. The pull-up unit comprises one or more pull-up transistors, and the pull-down unit comprises one or more pull-down transistors. The number of the pull-up transistors is different from the number of the pull-down transistors.