Asymmetrical Landing Pad Insulation for Semiconductor Reliability
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Solution Overview
Problem
In semiconductor devices, the down-scaling of interconnection lines and contact plugs leads to increased resistance and potential neck phenomenon in landing pads, causing improper formation and varying resistance issues due to the need for precise etching and insulation patterns.
Innovation Solution
The semiconductor device incorporates asymmetrical landing pad insulation patterns, such as stair-shaped designs, and air spacers to prevent excessive etching and maintain conductivity, ensuring proper formation and reduced resistance by controlling the etching process with selective etch rates for insulating and conductive materials.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If down-scaling of interconnection lines and contact plugs is implemented to increase integration density, then device integration is improved, but resistance increases and neck phenomenon occurs in landing pads
Solution Approach 1:
The patent applies asymmetry by forming the landing pad insulation pattern with different depths in different regions. Specifically, the insulation pattern has a first depth in a first region and a second depth greater than the first depth in a second region, creating an asymmetric structure that prevents excessive etching in certain areas while maintaining proper insulation, thereby preventing neck phenomenon and resistance variations in the landing pad
Solution Approach 2:
The patent implements local quality by providing different insulation depths in different regions of the landing pad. The first region receives insulation at a first depth while the second region receives insulation at a greater second depth, allowing each region to have optimized properties for its specific function, preventing both over-etching and under-etching in different areas
2Manufacturing precision
If precise etching is performed to form contact plugs between adjacent interconnection lines, then manufacturing precision is improved, but neck phenomenon and resistance variations occur in landing pads
Solution Approach 1:
The patent uses asymmetry in the landing pad insulation pattern depth to protect against over-etching during contact plug formation. By having different insulation depths in different regions, the pattern prevents excessive etching that would cause neck phenomenon while still allowing precise contact plug formation where needed
Solution Approach 2:
The patent applies beforehand cushioning by forming the asymmetric landing pad insulation pattern prior to contact plug formation. This pre-formed insulation structure acts as a protective cushion that prevents over-etching during subsequent processing steps, ensuring consistent landing pad resistance
Data Source
AI summary
A semiconductor device includes a substrate with an active region, a plurality of conductive line structures on the substrate, an insulating layer separating the plurality of conductive line structures from the substrate, a contact plug between every two adjacent conductive line structures, an insulating spacer structure between each conductive line structure and a corresponding contact plug, a landing pad connected to each contact plug, and a landing pad insulation pattern having an asymmetrical shape based on a vertical axis of the landing pad that extends along a normal to the substrate. The landing pad insulation pattern includes a first portion overlapping the conductive line structures and a second portion overlapping the contact plug, the first and second portions being on opposite sides of the vertical axis.