Asymmetrical LDD Layout for RF Semiconductor Resistance Reduction

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Solution Overview

Problem

Current RF devices face challenges due to higher resistance and large parasitic capacitance, which affect their overall performance.

Innovation Solution

The method involves fabricating a semiconductor device with a substrate having high-voltage and low-voltage regions, forming asymmetrical lightly doped drains (LDDs) adjacent to gate structures on these regions, and using a tilt angle ion implantation process to optimize the LDD structures.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional RF device structures are used, then manufacturing is simpler, but resistance is higher and parasitic capacitance is larger

Engineering Contradiction:
Improvedevice performanceVSAvoidLDD structure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies asymmetry by forming asymmetrical LDD structures where the first LDD and second LDD have different doping concentrations or geometries, and the third LDD and fourth LDD have different doping concentrations or geometries. This asymmetric design optimizes the electric field distribution to reduce parasitic capacitance and resistance, directly addressing the performance limitations of conventional symmetrical structures.

Inventive Principle:
Principle #4Asymmetry

Solution Approach 2:

The patent implements local quality by creating different LDD structures in different regions of the device. The first and second LDDs adjacent to the first gate structure have different properties from the third and fourth LDDs adjacent to the second gate structure. This localized differentiation allows optimization of specific regions to reduce parasitic effects while maintaining overall device functionality.

Inventive Principle:
Principle #3Local quality

2Reliability

If asymmetrical LDD structures are formed, then parasitic capacitance and resistance are reduced, but fabrication process becomes more complex

Engineering Contradiction:
Improvecut-off frequency and oscillation frequencyVSAvoidfabrication process
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The patent applies segmentation by dividing the LDD formation into multiple distinct stages: first forming the first LDD and second LDD with specific doping parameters, then separately forming the third LDD and fourth LDD with different doping parameters. This segmented approach allows precise control over each LDD's electrical characteristics while using standard fabrication techniques, making the complex asymmetric structure manufacturable.

Inventive Principle:
Principle #1Segmentation

3Speed

If LDD structures are optimized for frequency performance, then cut-off frequency increases, but breakdown voltage may be affected

Engineering Contradiction:
Improvecut-off frequencyVSAvoidbreakdown voltage
Core Design Contradiction:
SpeedVSStrength

Solution Approach 1:

The patent employs parameter changes by systematically varying doping concentrations, LDD lengths, and spacing dimensions to achieve optimal performance. The first and second LDDs have different doping concentrations from the third and fourth LDDs, allowing independent optimization of frequency characteristics and breakdown voltage. This multi-parameter adjustment enables simultaneous improvement of both speed and strength characteristics.

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach improves the robustness and performance of RF devices by reducing resistance and parasitic capacitance, enhancing the cut-off frequency and maximum oscillation frequency while maintaining high breakdown voltage and low leakage.

Implementation Method 1

using a tilt angle ion implantation process to optimize the LDD structures

Methodology Applied
Scientific EffectIon implantation: Ion Implantation

Data Source

PatentUS20250142854A1Semiconductor device and method for fabricating the same
Publication Date: 2025.05.01 UNITED MICROELECTRONICS CORP
  • US20250142854A1 patent drawing
  • US20250142854A1 patent drawing
  • US20250142854A1 patent drawing

AI summary

A method for fabricating semiconductor device includes the steps of first providing a substrate having a high-voltage (HV) region and a low-voltage (LV) region, forming a first gate structure on the HV region and a second gate structure on the LV region, forming a first lightly doped drain (LDD) adjacent to one side of the first gate structure and a second LDD adjacent to another side of the first gate structure, and then forming a third lightly doped drain (LDD) adjacent to one side of the second gate structure and a fourth LDD adjacent to another side of the second gate structure. Preferably, the first LDD and the second LDD are asymmetrical, the third LDD and the fourth LDD are asymmetrical, and the second LDD and the third LDD are symmetrical.