Asymmetrical Memory Management Circuitry for High Bandwidth Access
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Solution Overview
Problem
Current memory management systems face challenges in providing high bandwidth while maintaining a compact form factor and low power consumption, especially in mobile devices, as adding more memory channels increases size and complexity, and existing solutions like in-package memory may not meet capacity and bandwidth requirements effectively.
Innovation Solution
The implementation of asymmetrical memory management circuitry that dynamically allocates memory access between in-package and off-package memory, allowing concurrent access to aggregate bandwidth, thereby synthesizing a high bandwidth cache or memory region, and statically allocating system memory to optimize capacity and bandwidth usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If more memory channels are added to increase bandwidth, then memory bandwidth is improved, but device size and complexity increase
Solution Approach 1:
The patent combines in-package memory and off-package memory into a unified memory system, merging their bandwidth capabilities to achieve high memory bandwidth without adding multiple separate memory channels. The asymmetrical memory management circuitry integrates both memory types and coordinates their operation as a single cohesive system.
Solution Approach 2:
The memory system serves multiple functions by using in-package memory for high-bandwidth applications and off-package memory for capacity storage, allowing the same memory infrastructure to handle different workload requirements. The asymmetrical memory management enables the system to dynamically allocate requests to appropriate memory types based on bandwidth and capacity needs.
2Productivity
If in-package memory is used to increase bandwidth, then memory bandwidth is improved, but capacity and cost increase
Solution Approach 1:
The patent applies different memory types to different functional requirements: in-package memory is used specifically for high-bandwidth local access, while off-package memory provides bulk capacity. This local quality differentiation ensures that high bandwidth is provided only where needed, rather than uniformly across all memory operations.
Solution Approach 2:
The memory system is segmented into two distinct parts with different characteristics: in-package memory for bandwidth-critical operations and off-package memory for capacity-critical operations. The asymmetrical memory management circuitry segments memory requests and directs them to the appropriate memory type, preventing unnecessary use of expensive in-package memory for capacity storage.
3Device complexity
If symmetrical memory allocation is used, then simplicity is maintained, but bandwidth optimization is limited
Solution Approach 1:
The patent implements asymmetrical memory management that recognizes and exploits the different characteristics of in-package and off-package memory. Rather than treating all memory uniformly, the system uses asymmetrical allocation strategies that match memory requests to the appropriate memory type based on bandwidth requirements, achieving optimal bandwidth utilization.
Solution Approach 2:
The memory management system dynamically allocates memory requests to in-package or off-package memory based on real-time bandwidth requirements and memory availability. This dynamic allocation allows the system to adapt to varying workload demands, providing high bandwidth when needed while maintaining simplicity in normal operation.
Data Source
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AI summary
Described herein are embodiments of asymmetric memory management to enable high bandwidth accesses. In embodiments, a high bandwidth cache or high bandwidth region can be synthesized using the bandwidth capabilities of more than one memory source. In one embodiment, memory management circuitry includes input/output (I/O) circuitry coupled with a first and second memory. The I/O circuitry is to receive memory access requests. The memory management circuitry includes logic to determine if the memory access requests are for data in a first region of system memory or a second region of system memory, and in response to a determination that one of the memory access requests is to the first region and a second of the memory access requests is to the second region, access data in the first region from the cache of the first memory and concurrently access data in the second region from the second memory.