Asymmetrical Memory Partitioning for Network Switch Latency
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Solution Overview
Problem
Network switches face latency issues due to the time-consuming process of storing packets and related information in memory buffers, particularly when multiple input sources compete for access, leading to inefficiencies in data absorption and routing.
Innovation Solution
Implementing an asymmetrical partitioning scheme for memory buffers, where packet data and control structures are stored separately, with packet data in fewer partitions and control structures in more partitions, optimizing access times based on port periods and data lengths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If packets are stored in memory buffers for routing, then packet routing functionality is achieved, but processing latency increases
Solution Approach 1:
The memory buffer is divided into multiple partitions, with each partition dedicated to specific output ports. This segmentation allows parallel access to different partitions by different input sources, eliminating the need for time-division multiplexing and reducing packet storage latency while maintaining reliable routing functionality.
Solution Approach 2:
The patent transitions from a single-dimension time-division access model to a multi-dimension spatial partitioning model. By organizing memory buffers into multiple concurrent partitions that can be accessed simultaneously, the system adds a spatial dimension to memory access, thereby reducing latency without sacrificing routing reliability.
2Productivity
If multiple input sources access the memory buffer simultaneously, then data absorption capacity increases, but access conflict and latency increase
Solution Approach 1:
The memory buffer is segmented into multiple partitions, each accessible by specific input sources. This allows multiple input sources to access different partitions simultaneously without conflict, increasing overall data absorption capacity while maintaining low access latency for each source.
Solution Approach 2:
Each memory partition is optimized for specific input-output port combinations, creating local quality variations in the memory architecture. This allows each partition to be accessed efficiently by its designated sources, improving overall system productivity without introducing access conflicts.
3Speed
If the number of memory buffer partitions is increased, then access parallelism improves, but memory complexity increases
Solution Approach 1:
The memory buffer is divided into a manageable number of partitions that balances access parallelism with implementation complexity. This segmentation enables concurrent access by multiple sources while keeping the partition count practical for hardware implementation.
Solution Approach 2:
The system optimizes the number of partitions as a key parameter to achieve the desired balance between access speed and complexity. By carefully selecting the partition count based on specific performance requirements, the system maximizes parallelism while controlling memory buffer complexity.
Data Source
AI summary
Disclosed are various embodiments that provide an architecture of memory buffers for a network component configured to process packets. A network component may receive a packet, the packet being associated with a control structure and packet data, an input port set and an output port set. The network component determines one of a plurality of control structure memory partitions for writing the control structure, the one of the plurality of control structure memory partitions being determined based at least upon the input port set and the output port set; and determines one of a plurality of packet data memory partitions for writing the packet data, the one of the plurality of packet data memory partitions being determined independently of the input port set.